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351 lines
9.7 KiB
351 lines
9.7 KiB
/*
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* Copyright © 2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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/** @file gem_exec_store.c
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*
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* Simplest non-NOOP only batch with verification.
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*/
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#include "igt.h"
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#include "igt_device.h"
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#include "igt_gt.h"
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#include <strings.h>
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#define LOCAL_I915_EXEC_BSD_SHIFT (13)
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#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
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#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
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static void store_dword(int fd, const struct intel_execution_engine2 *e)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_exec_object2 obj[2];
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struct drm_i915_gem_relocation_entry reloc;
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struct drm_i915_gem_execbuffer2 execbuf;
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uint32_t batch[16];
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int i;
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igt_require(gem_class_can_store_dword(fd, e->class));
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intel_detect_and_clear_missed_interrupts(fd);
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(obj);
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execbuf.buffer_count = 2;
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execbuf.flags = e->flags;
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if (gen > 3 && gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[1].handle = gem_create(fd, 4096);
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memset(&reloc, 0, sizeof(reloc));
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reloc.target_handle = obj[0].handle;
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reloc.presumed_offset = 0;
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reloc.offset = sizeof(uint32_t);
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reloc.delta = 0;
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reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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obj[1].relocs_ptr = to_user_pointer(&reloc);
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obj[1].relocation_count = 1;
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i = 0;
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batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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batch[++i] = 0;
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batch[++i] = 0;
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} else if (gen >= 4) {
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batch[++i] = 0;
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batch[++i] = 0;
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reloc.offset += sizeof(uint32_t);
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} else {
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batch[i]--;
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batch[++i] = 0;
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}
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batch[++i] = 0xc0ffee;
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batch[++i] = MI_BATCH_BUFFER_END;
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gem_write(fd, obj[1].handle, 0, batch, sizeof(batch));
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gem_execbuf(fd, &execbuf);
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gem_close(fd, obj[1].handle);
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gem_read(fd, obj[0].handle, 0, batch, sizeof(batch));
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gem_close(fd, obj[0].handle);
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igt_assert_eq(*batch, 0xc0ffee);
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igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
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}
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#define PAGES 1
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static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
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unsigned int flags)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_exec_object2 *obj;
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struct drm_i915_gem_relocation_entry *reloc;
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struct drm_i915_gem_execbuffer2 execbuf;
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#define NCACHELINES (4096/64)
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uint32_t *batch;
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int i;
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reloc = calloc(NCACHELINES, sizeof(*reloc));
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igt_assert(reloc);
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igt_require(gem_class_can_store_dword(fd, e->class));
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intel_detect_and_clear_missed_interrupts(fd);
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffer_count = flags & PAGES ? NCACHELINES + 1 : 2;
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execbuf.flags = e->flags;
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if (gen > 3 && gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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obj = calloc(execbuf.buffer_count, sizeof(*obj));
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igt_assert(obj);
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for (i = 0; i < execbuf.buffer_count; i++)
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obj[i].handle = gem_create(fd, 4096);
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obj[i-1].relocs_ptr = to_user_pointer(reloc);
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obj[i-1].relocation_count = NCACHELINES;
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execbuf.buffers_ptr = to_user_pointer(obj);
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batch = gem_mmap__cpu(fd, obj[i-1].handle, 0, 4096, PROT_WRITE);
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i = 0;
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for (unsigned n = 0; n < NCACHELINES; n++) {
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reloc[n].target_handle = obj[n % (execbuf.buffer_count-1)].handle;
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reloc[n].presumed_offset = -1;
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reloc[n].offset = (i + 1)*sizeof(uint32_t);
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reloc[n].delta = 4 * (n * 16 + n % 16);
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reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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batch[++i] = 0;
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batch[++i] = 0;
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} else if (gen >= 4) {
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batch[++i] = 0;
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batch[++i] = 0;
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reloc[n].offset += sizeof(uint32_t);
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} else {
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batch[i]--;
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batch[++i] = 0;
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}
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batch[++i] = n | ~n << 16;
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i++;
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}
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batch[i++] = MI_BATCH_BUFFER_END;
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igt_assert(i < 4096 / sizeof(*batch));
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munmap(batch, 4096);
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gem_execbuf(fd, &execbuf);
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for (unsigned n = 0; n < NCACHELINES; n++) {
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uint32_t result;
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gem_read(fd, reloc[n].target_handle, reloc[n].delta,
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&result, sizeof(result));
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igt_assert_eq_u32(result, n | ~n << 16);
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}
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free(reloc);
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for (unsigned n = 0; n < execbuf.buffer_count; n++)
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gem_close(fd, obj[n].handle);
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free(obj);
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igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
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}
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static void store_all(int fd)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_exec_object2 obj[2];
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struct intel_execution_engine2 *engine;
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struct drm_i915_gem_relocation_entry reloc[32];
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struct drm_i915_gem_execbuffer2 execbuf;
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unsigned engines[16], permuted[16];
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uint32_t batch[16];
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uint64_t offset;
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unsigned nengine;
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int value;
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int i, j;
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(obj);
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execbuf.buffer_count = 2;
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if (gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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memset(reloc, 0, sizeof(reloc));
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[1].handle = gem_create(fd, 4096);
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obj[1].relocation_count = 1;
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offset = sizeof(uint32_t);
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i = 0;
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batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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batch[++i] = 0;
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batch[++i] = 0;
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} else if (gen >= 4) {
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batch[++i] = 0;
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batch[++i] = 0;
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offset += sizeof(uint32_t);
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} else {
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batch[i]--;
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batch[++i] = 0;
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}
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batch[value = ++i] = 0xc0ffee;
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batch[++i] = MI_BATCH_BUFFER_END;
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nengine = 0;
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intel_detect_and_clear_missed_interrupts(fd);
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__for_each_physical_engine(fd, engine) {
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if (!gem_class_can_store_dword(fd, engine->class))
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continue;
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igt_assert(2*(nengine+1)*sizeof(batch) <= 4096);
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execbuf.flags &= ~ENGINE_MASK;
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execbuf.flags |= engine->flags;
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j = 2*nengine;
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reloc[j].target_handle = obj[0].handle;
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reloc[j].presumed_offset = ~0;
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reloc[j].offset = j*sizeof(batch) + offset;
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reloc[j].delta = nengine*sizeof(uint32_t);
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reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
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batch[value] = 0xdeadbeef;
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gem_write(fd, obj[1].handle, j*sizeof(batch),
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batch, sizeof(batch));
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execbuf.batch_start_offset = j*sizeof(batch);
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gem_execbuf(fd, &execbuf);
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j = 2*nengine + 1;
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reloc[j].target_handle = obj[0].handle;
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reloc[j].presumed_offset = ~0;
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reloc[j].offset = j*sizeof(batch) + offset;
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reloc[j].delta = nengine*sizeof(uint32_t);
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reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
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batch[value] = nengine;
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gem_write(fd, obj[1].handle, j*sizeof(batch),
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batch, sizeof(batch));
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execbuf.batch_start_offset = j*sizeof(batch);
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gem_execbuf(fd, &execbuf);
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engines[nengine++] = engine->flags;
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}
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gem_sync(fd, obj[1].handle);
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for (i = 0; i < nengine; i++) {
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obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
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execbuf.batch_start_offset = 2*i*sizeof(batch);
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memcpy(permuted, engines, nengine*sizeof(engines[0]));
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igt_permute_array(permuted, nengine, igt_exchange_int);
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for (j = 0; j < nengine; j++) {
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execbuf.flags &= ~ENGINE_MASK;
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execbuf.flags |= permuted[j];
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gem_execbuf(fd, &execbuf);
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}
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obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
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execbuf.batch_start_offset = (2*i+1)*sizeof(batch);
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execbuf.flags &= ~ENGINE_MASK;
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execbuf.flags |= engines[i];
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gem_execbuf(fd, &execbuf);
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}
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gem_close(fd, obj[1].handle);
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gem_read(fd, obj[0].handle, 0, engines, sizeof(engines));
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gem_close(fd, obj[0].handle);
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for (i = 0; i < nengine; i++)
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igt_assert_eq_u32(engines[i], i);
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igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
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}
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static int print_welcome(int fd)
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{
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uint16_t devid = intel_get_drm_devid(fd);
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const struct intel_device_info *info = intel_get_device_info(devid);
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int err;
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igt_info("Running on %s (pci-id %04x, gen %d)\n",
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info->codename, devid, ffs(info->gen));
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igt_info("Can use MI_STORE_DWORD(virtual)? %s\n",
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gem_can_store_dword(fd, 0) ? "yes" : "no");
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err = 0;
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if (drmIoctl(fd, DRM_IOCTL_I915_GEM_THROTTLE, 0))
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err = -errno;
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igt_info("GPU operation? %s [errno=%d]\n",
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err == 0 ? "yes" : "no", err);
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return ffs(info->gen);
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}
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igt_main
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{
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const struct intel_execution_engine2 *e;
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int fd;
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igt_fixture {
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int gen;
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fd = drm_open_driver(DRIVER_INTEL);
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gen = print_welcome(fd);
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if (gen > 3 && gen < 6) /* ctg and ilk need secure batches */
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igt_device_set_master(fd);
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igt_require_gem(fd);
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igt_require(gem_can_store_dword(fd, 0));
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igt_fork_hang_detector(fd);
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}
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__for_each_physical_engine(fd, e) {
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igt_subtest_f("basic-%s", e->name)
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store_dword(fd, e);
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igt_subtest_f("cachelines-%s", e->name)
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store_cachelines(fd, e, 0);
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igt_subtest_f("pages-%s", e->name)
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store_cachelines(fd, e, PAGES);
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}
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igt_subtest("basic-all")
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store_all(fd);
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igt_fixture {
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igt_stop_hang_detector();
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close(fd);
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}
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}
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