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268 lines
7.0 KiB
268 lines
7.0 KiB
/*
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* Copyright © 2008-9 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#include "config.h"
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/ioctl.h>
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#include <pthread.h>
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#include "drm.h"
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#include "igt.h"
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#include "igt_x86.h"
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#define PAGE_SIZE 4096
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#define CACHELINE 64
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#define OBJECT_SIZE (128*1024) /* restricted to 1MiB alignment on i915 fences */
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/* Before introduction of the LRU list for fences, allocation of a fence for a page
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* fault would use the first inactive fence (i.e. in preference one with no outstanding
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* GPU activity, or it would wait on the first to finish). Given the choice, it would simply
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* reuse the fence that had just been allocated for the previous page-fault - the worst choice
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* when copying between two buffers and thus constantly swapping fences.
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*/
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struct test {
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int fd;
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int tiling;
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int num_surfaces;
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};
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static void *
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bo_create (int fd, int tiling)
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{
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uint32_t handle;
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void *ptr;
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handle = gem_create(fd, OBJECT_SIZE);
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/* dirty cpu caches a bit ... */
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ptr = gem_mmap__cpu(fd, handle, 0, OBJECT_SIZE,
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PROT_READ | PROT_WRITE);
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memset(ptr, 0, OBJECT_SIZE);
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munmap(ptr, OBJECT_SIZE);
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gem_set_tiling(fd, handle, tiling, 1024);
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ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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gem_close(fd, handle);
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return ptr;
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}
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static void *
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bo_copy (void *_arg)
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{
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struct test *t = (struct test *)_arg;
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int fd = t->fd;
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int n;
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char *a, *b;
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a = bo_create (fd, t->tiling);
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b = bo_create (fd, t->tiling);
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for (n = 0; n < 1000; n++) {
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memcpy (a, b, OBJECT_SIZE);
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sched_yield ();
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}
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munmap(a, OBJECT_SIZE);
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munmap(b, OBJECT_SIZE);
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return NULL;
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}
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static void copy_wc_page(void *dst, const void *src)
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{
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igt_memcpy_from_wc(dst, src, PAGE_SIZE);
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}
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static void copy_wc_cacheline(void *dst, const void *src)
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{
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igt_memcpy_from_wc(dst, src, CACHELINE);
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}
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static void
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_bo_write_verify(struct test *t)
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{
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int fd = t->fd;
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int i, k;
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uint32_t **s;
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unsigned int dwords = OBJECT_SIZE >> 2;
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const char *tile_str[] = { "none", "x", "y" };
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uint32_t tmp[PAGE_SIZE/sizeof(uint32_t)];
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igt_assert(t->tiling >= 0 && t->tiling <= I915_TILING_Y);
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igt_assert_lt(0, t->num_surfaces);
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s = calloc(sizeof(*s), t->num_surfaces);
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igt_assert(s);
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for (k = 0; k < t->num_surfaces; k++)
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s[k] = bo_create(fd, t->tiling);
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for (k = 0; k < t->num_surfaces; k++) {
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uint32_t *a = s[k];
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a[0] = 0xdeadbeef;
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igt_assert_f(a[0] == 0xdeadbeef,
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"tiling %s: write failed at start (%x)\n",
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tile_str[t->tiling], a[0]);
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a[dwords - 1] = 0xc0ffee;
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igt_assert_f(a[dwords - 1] == 0xc0ffee,
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"tiling %s: write failed at end (%x)\n",
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tile_str[t->tiling], a[dwords - 1]);
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for (i = 0; i < dwords; i += CACHELINE/sizeof(uint32_t)) {
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for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
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a[i + j] = ~(i + j);
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copy_wc_cacheline(tmp, a + i);
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for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
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igt_assert_f(tmp[j] == ~(i+ j),
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"tiling %s: write failed at %d (%x)\n",
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tile_str[t->tiling], i + j, tmp[j]);
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for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
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a[i + j] = i + j;
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}
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for (i = 0; i < dwords; i += PAGE_SIZE/sizeof(uint32_t)) {
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copy_wc_page(tmp, a + i);
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for (int j = 0; j < PAGE_SIZE/sizeof(uint32_t); j++) {
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igt_assert_f(tmp[j] == i + j,
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"tiling %s: verify failed at %d (%x)\n",
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tile_str[t->tiling], i + j, tmp[j]);
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}
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}
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}
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for (k = 0; k < t->num_surfaces; k++)
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munmap(s[k], OBJECT_SIZE);
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free(s);
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}
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static void *
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bo_write_verify(void *_arg)
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{
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struct test *t = (struct test *)_arg;
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int i;
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for (i = 0; i < 10; i++)
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_bo_write_verify(t);
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return 0;
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}
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static int run_test(int threads_per_fence, void *f, int tiling,
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int surfaces_per_thread)
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{
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struct test t;
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pthread_t *threads;
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int n, num_fences, num_threads;
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t.fd = drm_open_driver(DRIVER_INTEL);
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t.tiling = tiling;
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t.num_surfaces = surfaces_per_thread;
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num_fences = gem_available_fences(t.fd);
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igt_assert_lt(0, num_fences);
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num_threads = threads_per_fence * num_fences;
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igt_info("%s: threads %d, fences %d, tiling %d, surfaces per thread %d\n",
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f == bo_copy ? "copy" : "write-verify", num_threads,
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num_fences, tiling, surfaces_per_thread);
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if (threads_per_fence) {
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threads = calloc(sizeof(*threads), num_threads);
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igt_assert(threads != NULL);
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for (n = 0; n < num_threads; n++)
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pthread_create (&threads[n], NULL, f, &t);
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for (n = 0; n < num_threads; n++)
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pthread_join (threads[n], NULL);
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free(threads);
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} else {
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void *(*func)(void *) = f;
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igt_assert(func(&t) == (void *)0);
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}
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close(t.fd);
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return 0;
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}
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igt_main
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{
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igt_skip_on_simulation();
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igt_subtest("bo-write-verify-none")
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igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) == 0);
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igt_subtest("bo-write-verify-x")
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igt_assert(run_test(0, bo_write_verify, I915_TILING_X, 80) == 0);
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igt_subtest("bo-write-verify-y")
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igt_assert(run_test(0, bo_write_verify, I915_TILING_Y, 80) == 0);
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igt_subtest("bo-write-verify-threaded-none")
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igt_assert(run_test(5, bo_write_verify, I915_TILING_NONE, 2) == 0);
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igt_subtest("bo-write-verify-threaded-x") {
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igt_assert(run_test(2, bo_write_verify, I915_TILING_X, 2) == 0);
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igt_assert(run_test(5, bo_write_verify, I915_TILING_X, 2) == 0);
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igt_assert(run_test(10, bo_write_verify, I915_TILING_X, 2) == 0);
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igt_assert(run_test(20, bo_write_verify, I915_TILING_X, 2) == 0);
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}
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igt_subtest("bo-write-verify-threaded-y") {
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igt_assert(run_test(2, bo_write_verify, I915_TILING_Y, 2) == 0);
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igt_assert(run_test(5, bo_write_verify, I915_TILING_Y, 2) == 0);
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igt_assert(run_test(10, bo_write_verify, I915_TILING_Y, 2) == 0);
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igt_assert(run_test(20, bo_write_verify, I915_TILING_Y, 2) == 0);
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}
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igt_subtest("bo-copy")
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igt_assert(run_test(1, bo_copy, I915_TILING_X, 1) == 0);
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}
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