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445 lines
11 KiB
445 lines
11 KiB
/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This header is BSD licensed so anyone can use the definitions
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* to implement compatible drivers/servers:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of IBM nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef VIRTIO_GPU_HW_H
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#define VIRTIO_GPU_HW_H
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#include <linux/types.h>
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/*
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* VIRTIO_GPU_CMD_CTX_*
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* VIRTIO_GPU_CMD_*_3D
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*/
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#define VIRTIO_GPU_F_VIRGL 0
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/*
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* VIRTIO_GPU_CMD_GET_EDID
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*/
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#define VIRTIO_GPU_F_EDID 1
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/*
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* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
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*/
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#define VIRTIO_GPU_F_RESOURCE_UUID 2
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/*
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* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
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*/
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#define VIRTIO_GPU_F_RESOURCE_BLOB 3
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enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_UNDEFINED = 0,
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/* 2d commands */
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VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
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VIRTIO_GPU_CMD_RESOURCE_UNREF,
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VIRTIO_GPU_CMD_SET_SCANOUT,
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VIRTIO_GPU_CMD_RESOURCE_FLUSH,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
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VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
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VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
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VIRTIO_GPU_CMD_GET_CAPSET_INFO,
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VIRTIO_GPU_CMD_GET_CAPSET,
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VIRTIO_GPU_CMD_GET_EDID,
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VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
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VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
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/* 3d commands */
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VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
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VIRTIO_GPU_CMD_CTX_DESTROY,
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VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
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VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
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VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
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VIRTIO_GPU_CMD_SUBMIT_3D,
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VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
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VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
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/* cursor commands */
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VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
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VIRTIO_GPU_CMD_MOVE_CURSOR,
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/* success responses */
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VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
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VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET,
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VIRTIO_GPU_RESP_OK_EDID,
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VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
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VIRTIO_GPU_RESP_OK_MAP_INFO,
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/* error responses */
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VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
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VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
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VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
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};
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enum virtio_gpu_shm_id {
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VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
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/*
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* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
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* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
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*/
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VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
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};
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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struct virtio_gpu_ctrl_hdr {
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__le32 type;
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__le32 flags;
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__le64 fence_id;
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__le32 ctx_id;
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__le32 padding;
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};
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/* data passed in the cursor vq */
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struct virtio_gpu_cursor_pos {
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__le32 scanout_id;
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__le32 x;
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__le32 y;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
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struct virtio_gpu_update_cursor {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_cursor_pos pos; /* update & move */
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__le32 resource_id; /* update only */
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__le32 hot_x; /* update only */
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__le32 hot_y; /* update only */
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__le32 padding;
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};
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/* data passed in the control vq, 2d related */
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struct virtio_gpu_rect {
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__le32 x;
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__le32 y;
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__le32 width;
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__le32 height;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
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struct virtio_gpu_resource_unref {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
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struct virtio_gpu_resource_create_2d {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 format;
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__le32 width;
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__le32 height;
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};
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/* VIRTIO_GPU_CMD_SET_SCANOUT */
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struct virtio_gpu_set_scanout {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le32 scanout_id;
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__le32 resource_id;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
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struct virtio_gpu_resource_flush {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
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struct virtio_gpu_transfer_to_host_2d {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le64 offset;
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__le32 resource_id;
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__le32 padding;
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};
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struct virtio_gpu_mem_entry {
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__le64 addr;
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__le32 length;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
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struct virtio_gpu_resource_attach_backing {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 nr_entries;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
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struct virtio_gpu_resource_detach_backing {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
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#define VIRTIO_GPU_MAX_SCANOUTS 16
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struct virtio_gpu_resp_display_info {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_display_one {
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struct virtio_gpu_rect r;
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__le32 enabled;
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__le32 flags;
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} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
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};
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/* data passed in the control vq, 3d related */
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struct virtio_gpu_box {
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__le32 x, y, z;
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__le32 w, h, d;
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};
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/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
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struct virtio_gpu_transfer_host_3d {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_box box;
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__le64 offset;
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__le32 resource_id;
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__le32 level;
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__le32 stride;
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__le32 layer_stride;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
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#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
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struct virtio_gpu_resource_create_3d {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 target;
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__le32 format;
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__le32 bind;
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__le32 width;
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__le32 height;
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__le32 depth;
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__le32 array_size;
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__le32 last_level;
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__le32 nr_samples;
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__le32 flags;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_CTX_CREATE */
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struct virtio_gpu_ctx_create {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 nlen;
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__le32 padding;
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char debug_name[64];
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};
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/* VIRTIO_GPU_CMD_CTX_DESTROY */
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struct virtio_gpu_ctx_destroy {
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struct virtio_gpu_ctrl_hdr hdr;
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};
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/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
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struct virtio_gpu_ctx_resource {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_SUBMIT_3D */
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struct virtio_gpu_cmd_submit {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 size;
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__le32 padding;
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};
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#define VIRTIO_GPU_CAPSET_VIRGL 1
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#define VIRTIO_GPU_CAPSET_VIRGL2 2
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/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
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struct virtio_gpu_get_capset_info {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 capset_index;
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__le32 padding;
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};
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/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
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struct virtio_gpu_resp_capset_info {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 capset_id;
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__le32 capset_max_version;
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__le32 capset_max_size;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_GET_CAPSET */
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struct virtio_gpu_get_capset {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 capset_id;
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__le32 capset_version;
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};
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/* VIRTIO_GPU_RESP_OK_CAPSET */
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struct virtio_gpu_resp_capset {
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struct virtio_gpu_ctrl_hdr hdr;
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__u8 capset_data[];
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};
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/* VIRTIO_GPU_CMD_GET_EDID */
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struct virtio_gpu_cmd_get_edid {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 scanout;
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__le32 padding;
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};
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/* VIRTIO_GPU_RESP_OK_EDID */
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struct virtio_gpu_resp_edid {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 size;
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__le32 padding;
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__u8 edid[1024];
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};
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#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
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struct virtio_gpu_config {
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__le32 events_read;
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__le32 events_clear;
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__le32 num_scanouts;
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__le32 num_capsets;
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};
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/* simple formats for fbcon/X use */
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enum virtio_gpu_formats {
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VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
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VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
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VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
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VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
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VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
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VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
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VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
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VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
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};
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/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
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struct virtio_gpu_resource_assign_uuid {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
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struct virtio_gpu_resp_resource_uuid {
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struct virtio_gpu_ctrl_hdr hdr;
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__u8 uuid[16];
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};
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
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struct virtio_gpu_resource_create_blob {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
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#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
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#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
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#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
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#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
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#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
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/* zero is invalid blob mem */
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__le32 blob_mem;
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__le32 blob_flags;
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__le32 nr_entries;
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__le64 blob_id;
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__le64 size;
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/*
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* sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
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*/
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};
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/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
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struct virtio_gpu_set_scanout_blob {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le32 scanout_id;
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__le32 resource_id;
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__le32 width;
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__le32 height;
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__le32 format;
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__le32 padding;
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__le32 strides[4];
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__le32 offsets[4];
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};
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/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
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struct virtio_gpu_resource_map_blob {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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__le64 offset;
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};
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/* VIRTIO_GPU_RESP_OK_MAP_INFO */
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#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
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#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
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#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
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#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
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#define VIRTIO_GPU_MAP_CACHE_WC 0x03
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struct virtio_gpu_resp_map_info {
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struct virtio_gpu_ctrl_hdr hdr;
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__u32 map_info;
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__u32 padding;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
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struct virtio_gpu_resource_unmap_blob {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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#endif
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