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419 lines
12 KiB
419 lines
12 KiB
//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISCV target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/MachineValueType.h"
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namespace llvm {
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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namespace RISCVII {
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enum {
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InstFormatPseudo = 0,
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InstFormatR = 1,
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InstFormatR4 = 2,
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InstFormatI = 3,
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InstFormatS = 4,
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InstFormatB = 5,
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InstFormatU = 6,
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InstFormatJ = 7,
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InstFormatCR = 8,
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InstFormatCI = 9,
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InstFormatCSS = 10,
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InstFormatCIW = 11,
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InstFormatCL = 12,
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InstFormatCS = 13,
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InstFormatCA = 14,
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InstFormatCB = 15,
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InstFormatCJ = 16,
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InstFormatOther = 17,
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InstFormatMask = 31,
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ConstraintOffset = 5,
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ConstraintMask = 0b1111
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};
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// Match with the definitions in RISCVInstrFormatsV.td
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enum RVVConstraintType {
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NoConstraint = 0,
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VS2Constraint = 0b0001,
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VS1Constraint = 0b0010,
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VMConstraint = 0b0100,
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OneInput = 0b1000,
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// Illegal instructions:
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//
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// * The destination vector register group for a masked vector instruction
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// cannot overlap the source mask register (v0), unless the destination vector
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// register is being written with a mask value (e.g., comparisons) or the
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// scalar result of a reduction.
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//
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// * Widening: The destination vector register group cannot overlap a source
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// vector register group of a different EEW
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//
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// * Narrowing: The destination vector register group cannot overlap the
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// first source vector register group
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//
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// * For vadc and vsbc, an illegal instruction exception is raised if the
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// destination vector register is v0.
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//
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// * For vmadc and vmsbc, an illegal instruction exception is raised if the
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// destination vector register overlaps a source vector register group.
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//
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// * viota: An illegal instruction exception is raised if the destination
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// vector register group overlaps the source vector mask register. If the
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// instruction is masked, an illegal instruction exception is issued if the
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// destination vector register group overlaps v0.
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//
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// * v[f]slide[1]up: The destination vector register group for vslideup cannot
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// overlap the source vector register group.
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//
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// * vrgather: The destination vector register group cannot overlap with the
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// source vector register groups.
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//
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// * vcompress: The destination vector register group cannot overlap the
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// source vector register group or the source mask register
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WidenV = VS2Constraint | VS1Constraint | VMConstraint,
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WidenW = VS1Constraint | VMConstraint,
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WidenCvt = VS2Constraint | VMConstraint | OneInput,
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Narrow = VS2Constraint | VMConstraint,
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NarrowCvt = VS2Constraint | VMConstraint | OneInput,
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Vmadc = VS2Constraint | VS1Constraint,
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Iota = VS2Constraint | VMConstraint | OneInput,
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SlideUp = VS2Constraint | VMConstraint,
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Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
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Vcompress = VS2Constraint | VS1Constraint,
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};
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// RISC-V Specific Machine Operand Flags
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enum {
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MO_None = 0,
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MO_CALL = 1,
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MO_PLT = 2,
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MO_LO = 3,
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MO_HI = 4,
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MO_PCREL_LO = 5,
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MO_PCREL_HI = 6,
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MO_GOT_HI = 7,
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MO_TPREL_LO = 8,
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MO_TPREL_HI = 9,
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MO_TPREL_ADD = 10,
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MO_TLS_GOT_HI = 11,
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MO_TLS_GD_HI = 12,
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// Used to differentiate between target-specific "direct" flags and "bitmask"
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// flags. A machine operand can only have one "direct" flag, but can have
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// multiple "bitmask" flags.
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MO_DIRECT_FLAG_MASK = 15
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};
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} // namespace RISCVII
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namespace RISCVOp {
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enum OperandType : unsigned {
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OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
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OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
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OPERAND_UIMM5,
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OPERAND_UIMM12,
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OPERAND_SIMM12,
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OPERAND_UIMM20,
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OPERAND_UIMMLOG2XLEN,
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OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
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};
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} // namespace RISCVOp
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// Describes the predecessor/successor bits used in the FENCE instruction.
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namespace RISCVFenceField {
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enum FenceField {
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I = 8,
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O = 4,
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R = 2,
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W = 1
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};
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}
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// Describes the supported floating point rounding mode encodings.
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namespace RISCVFPRndMode {
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enum RoundingMode {
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RNE = 0,
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RTZ = 1,
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RDN = 2,
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RUP = 3,
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RMM = 4,
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DYN = 7,
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Invalid
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};
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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switch (RndMode) {
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default:
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llvm_unreachable("Unknown floating point rounding mode");
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case RISCVFPRndMode::RNE:
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return "rne";
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case RISCVFPRndMode::RTZ:
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return "rtz";
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case RISCVFPRndMode::RDN:
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return "rdn";
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case RISCVFPRndMode::RUP:
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return "rup";
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case RISCVFPRndMode::RMM:
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return "rmm";
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case RISCVFPRndMode::DYN:
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return "dyn";
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}
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}
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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return StringSwitch<RoundingMode>(Str)
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.Case("rne", RISCVFPRndMode::RNE)
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.Case("rtz", RISCVFPRndMode::RTZ)
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.Case("rdn", RISCVFPRndMode::RDN)
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.Case("rup", RISCVFPRndMode::RUP)
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.Case("rmm", RISCVFPRndMode::RMM)
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.Case("dyn", RISCVFPRndMode::DYN)
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.Default(RISCVFPRndMode::Invalid);
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}
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inline static bool isValidRoundingMode(unsigned Mode) {
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode::RNE:
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case RISCVFPRndMode::RTZ:
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case RISCVFPRndMode::RDN:
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case RISCVFPRndMode::RUP:
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case RISCVFPRndMode::RMM:
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case RISCVFPRndMode::DYN:
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return true;
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}
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}
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} // namespace RISCVFPRndMode
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namespace RISCVSysReg {
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struct SysReg {
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const char *Name;
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unsigned Encoding;
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const char *AltName;
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read, Write, Read-Only.
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// unsigned ReadWrite;
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// Privilege Mode: User, System or Machine.
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// unsigned Mode;
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// Check field name.
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// unsigned Extra;
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// Register number without the privilege bits.
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// unsigned Number;
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FeatureBitset FeaturesRequired;
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bool isRV32Only;
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bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
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// Not in 32-bit mode.
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if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
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return false;
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// No required feature associated with the system register.
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if (FeaturesRequired.none())
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return true;
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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};
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#define GET_SysRegsList_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVSysReg
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namespace RISCVABI {
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enum ABI {
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ABI_ILP32,
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ABI_ILP32F,
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ABI_ILP32D,
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ABI_ILP32E,
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ABI_LP64,
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ABI_LP64F,
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ABI_LP64D,
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ABI_Unknown
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};
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// Returns the target ABI, or else a StringError if the requested ABIName is
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// not supported for the given TT and FeatureBits combination.
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ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
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StringRef ABIName);
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ABI getTargetABI(StringRef ABIName);
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// Returns the register used to hold the stack pointer after realignment.
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MCRegister getBPReg();
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// Returns the register holding shadow call stack pointer.
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MCRegister getSCSPReg();
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} // namespace RISCVABI
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namespace RISCVFeatures {
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// Validates if the given combination of features are valid for the target
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// triple. Exits with report_fatal_error if not.
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void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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} // namespace RISCVFeatures
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namespace RISCVVMVTs {
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constexpr MVT vint8mf8_t = MVT::nxv1i8;
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constexpr MVT vint8mf4_t = MVT::nxv2i8;
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constexpr MVT vint8mf2_t = MVT::nxv4i8;
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constexpr MVT vint8m1_t = MVT::nxv8i8;
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constexpr MVT vint8m2_t = MVT::nxv16i8;
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constexpr MVT vint8m4_t = MVT::nxv32i8;
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constexpr MVT vint8m8_t = MVT::nxv64i8;
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constexpr MVT vint16mf4_t = MVT::nxv1i16;
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constexpr MVT vint16mf2_t = MVT::nxv2i16;
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constexpr MVT vint16m1_t = MVT::nxv4i16;
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constexpr MVT vint16m2_t = MVT::nxv8i16;
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constexpr MVT vint16m4_t = MVT::nxv16i16;
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constexpr MVT vint16m8_t = MVT::nxv32i16;
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constexpr MVT vint32mf2_t = MVT::nxv1i32;
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constexpr MVT vint32m1_t = MVT::nxv2i32;
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constexpr MVT vint32m2_t = MVT::nxv4i32;
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constexpr MVT vint32m4_t = MVT::nxv8i32;
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constexpr MVT vint32m8_t = MVT::nxv16i32;
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constexpr MVT vint64m1_t = MVT::nxv1i64;
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constexpr MVT vint64m2_t = MVT::nxv2i64;
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constexpr MVT vint64m4_t = MVT::nxv4i64;
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constexpr MVT vint64m8_t = MVT::nxv8i64;
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constexpr MVT vfloat16mf4_t = MVT::nxv1f16;
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constexpr MVT vfloat16mf2_t = MVT::nxv2f16;
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constexpr MVT vfloat16m1_t = MVT::nxv4f16;
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constexpr MVT vfloat16m2_t = MVT::nxv8f16;
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constexpr MVT vfloat16m4_t = MVT::nxv16f16;
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constexpr MVT vfloat16m8_t = MVT::nxv32f16;
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constexpr MVT vfloat32mf2_t = MVT::nxv1f32;
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constexpr MVT vfloat32m1_t = MVT::nxv2f32;
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constexpr MVT vfloat32m2_t = MVT::nxv4f32;
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constexpr MVT vfloat32m4_t = MVT::nxv8f32;
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constexpr MVT vfloat32m8_t = MVT::nxv16f32;
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constexpr MVT vfloat64m1_t = MVT::nxv1f64;
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constexpr MVT vfloat64m2_t = MVT::nxv2f64;
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constexpr MVT vfloat64m4_t = MVT::nxv4f64;
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constexpr MVT vfloat64m8_t = MVT::nxv8f64;
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constexpr MVT vbool1_t = MVT::nxv64i1;
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constexpr MVT vbool2_t = MVT::nxv32i1;
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constexpr MVT vbool4_t = MVT::nxv16i1;
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constexpr MVT vbool8_t = MVT::nxv8i1;
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constexpr MVT vbool16_t = MVT::nxv4i1;
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constexpr MVT vbool32_t = MVT::nxv2i1;
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constexpr MVT vbool64_t = MVT::nxv1i1;
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} // namespace RISCVVMVTs
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enum class RISCVVSEW {
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SEW_8 = 0,
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SEW_16,
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SEW_32,
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SEW_64,
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SEW_128,
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SEW_256,
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SEW_512,
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SEW_1024,
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};
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enum class RISCVVLMUL {
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LMUL_1 = 0,
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LMUL_2,
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LMUL_4,
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LMUL_8,
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LMUL_F8 = 5,
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LMUL_F4,
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LMUL_F2
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};
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namespace RISCVVType {
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// Is this a SEW value that can be encoded into the VTYPE format.
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inline static bool isValidSEW(unsigned SEW) {
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return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
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}
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// Is this a LMUL value that can be encoded into the VTYPE format.
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inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
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return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
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}
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// Encode VTYPE into the binary format used by the the VSETVLI instruction which
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// is used by our MC layer representation.
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//
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// Bits | Name | Description
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// -----+------------+------------------------------------------------
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// 7 | vma | Vector mask agnostic
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// 6 | vta | Vector tail agnostic
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// 5 | vlmul[2] | Fractional lmul?
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// 4:2 | vsew[2:0] | Standard element width (SEW) setting
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// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting
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//
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// TODO: This format will change for the V extensions spec v1.0.
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inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
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bool TailAgnostic, bool MaskAgnostic) {
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unsigned VLMULBits = static_cast<unsigned>(VLMUL);
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unsigned VSEWBits = static_cast<unsigned>(VSEW);
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unsigned VTypeI =
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((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
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if (TailAgnostic)
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VTypeI |= 0x40;
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if (MaskAgnostic)
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VTypeI |= 0x80;
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return VTypeI;
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}
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} // namespace RISCVVType
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namespace RISCVVPseudosTable {
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struct PseudoInfo {
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unsigned int Pseudo;
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unsigned int BaseInstr;
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uint8_t VLIndex;
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uint8_t SEWIndex;
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uint8_t MergeOpIndex;
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uint8_t VLMul;
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int getVLIndex() const { return static_cast<int8_t>(VLIndex); }
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int getSEWIndex() const { return static_cast<int8_t>(SEWIndex); }
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int getMergeOpIndex() const { return static_cast<int8_t>(MergeOpIndex); }
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};
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using namespace RISCV;
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#define GET_RISCVVPseudosTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVVPseudosTable
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} // namespace llvm
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#endif
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