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96 lines
3.6 KiB
96 lines
3.6 KiB
//===- ROCDLDialect.cpp - ROCDL IR Ops and Dialect registration -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the types and operation details for the ROCDL IR dialect in
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// MLIR, and the LLVM IR dialect. It also registers the dialect.
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//
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// The ROCDL dialect only contains GPU specific additions on top of the general
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// LLVM dialect.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/IR/Operation.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/SourceMgr.h"
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using namespace mlir;
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using namespace ROCDL;
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//===----------------------------------------------------------------------===//
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// Parsing for ROCDL ops
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//===----------------------------------------------------------------------===//
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// <operation> ::=
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// `llvm.amdgcn.buffer.load.* %rsrc, %vindex, %offset, %glc, %slc :
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// result_type`
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static ParseResult parseROCDLMubufLoadOp(OpAsmParser &parser,
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OperationState &result) {
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type type;
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if (parser.parseOperandList(ops, 5) || parser.parseColonType(type) ||
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parser.addTypeToList(type, result.types))
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return failure();
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MLIRContext *context = parser.getBuilder().getContext();
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auto int32Ty = LLVM::LLVMType::getInt32Ty(context);
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auto int1Ty = LLVM::LLVMType::getInt1Ty(context);
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auto i32x4Ty = LLVM::LLVMType::getVectorTy(int32Ty, 4);
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return parser.resolveOperands(ops,
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{i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
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parser.getNameLoc(), result.operands);
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}
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// <operation> ::=
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// `llvm.amdgcn.buffer.store.* %vdata, %rsrc, %vindex, %offset, %glc, %slc :
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// result_type`
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static ParseResult parseROCDLMubufStoreOp(OpAsmParser &parser,
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OperationState &result) {
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SmallVector<OpAsmParser::OperandType, 8> ops;
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Type type;
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if (parser.parseOperandList(ops, 6) || parser.parseColonType(type))
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return failure();
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MLIRContext *context = parser.getBuilder().getContext();
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auto int32Ty = LLVM::LLVMType::getInt32Ty(context);
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auto int1Ty = LLVM::LLVMType::getInt1Ty(context);
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auto i32x4Ty = LLVM::LLVMType::getVectorTy(int32Ty, 4);
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if (parser.resolveOperands(ops,
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{type, i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
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parser.getNameLoc(), result.operands))
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return failure();
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return success();
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}
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//===----------------------------------------------------------------------===//
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// ROCDLDialect initialization, type parsing, and registration.
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//===----------------------------------------------------------------------===//
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// TODO: This should be the llvm.rocdl dialect once this is supported.
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void ROCDLDialect::initialize() {
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addOperations<
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#define GET_OP_LIST
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#include "mlir/Dialect/LLVMIR/ROCDLOps.cpp.inc"
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>();
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// Support unknown operations because not all ROCDL operations are registered.
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allowUnknownOperations();
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}
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#define GET_OP_CLASSES
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#include "mlir/Dialect/LLVMIR/ROCDLOps.cpp.inc"
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