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125 lines
5.1 KiB
125 lines
5.1 KiB
VIXL Change Log
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===============
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* 1.13
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+ Improve code formatting and add tests using clang-format.
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+ Fix bugs in disassembly of unallocated instruction encodings.
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+ Fix some execution trace bugs, and add tests.
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+ Other small bug fixes and improvements.
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* 1.12
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+ Bug fixes for toolchain compatibility.
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* 1.11
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+ Fix bug in simulation of add with carry.
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+ Fix use-after-free bug in Literal handling.
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+ Build system updates for Android.
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+ Add option to run test.py under Valgrind.
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+ Other small bug fixes and improvements.
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* 1.10
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+ Improved support for externally managed literals.
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+ Reworked build and test infrastructure.
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+ Other small bug fixes and improvements.
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* 1.9
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+ Improved compatibility with Android build system.
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+ Improved compatibility with Clang toolchain.
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+ Added support for `umulh` instruction.
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+ Added support for `fcmpe` and `fccmpe` instructions.
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+ Other small bug fixes and improvements.
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* 1.8
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+ Complete NEON instruction set support.
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+ Support long branches using veneers.
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+ Improved handling of literal pools.
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+ Support some `ic` and `dc` cache op instructions.
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+ Support CRC32 instructions.
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+ Support half-precision floating point instructions.
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+ MacroAssembler support for `bfm`, `ubfm` and `sbfm`.
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+ Other small bug fixes and improvements.
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* 1.7
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+ Added support for `prfm` prefetch instructions.
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+ Added support for all `frint` instruction variants.
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+ Add support for disassembling as an offset from a given address.
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+ Fixed the disassembly of `movz` and `movn`.
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+ Provide static helpers for immediate generation.
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+ Provide helpers to create CPURegList from list unions or intersections.
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+ Improved register value tracing.
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+ Multithreading test fixes.
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+ Other small bug fixes and build system improvements.
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* 1.6
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+ Make literal pool management the responsibility of the macro assembler.
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+ Move code buffer management out of the Assembler.
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+ Support `ldrsw` for literals.
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+ Support binding a label to a specific offset.
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+ Add macro assembler support for load/store pair with arbitrary offset.
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+ Support Peek and Poke for CPURegLists.
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+ Fix disassembly of branch targets.
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+ Fix Decoder visitor insertion order.
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+ Separate Decoder visitors into const and non-const variants.
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+ Fix simulator for branches to tagged addresses.
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+ Add a VIM YouCompleteMe configuration file.
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+ Other small bug fixes and build system improvements.
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* 1.5
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+ Tagged pointer support.
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+ Implement support for exclusive access instructions.
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+ Implement support for `adrp` instruction.
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+ Faster code for logical immediate identification.
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+ Generate better code for immediates passed to shift-capable instructions.
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+ Allow explicit use of unscaled-offset loads and stores.
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+ Build and test infrastructure improvements.
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+ Corrected computation of cache line size.
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+ Fix simulation of `extr` instruction.
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+ Fixed a bug when moving kWMinInt to a register.
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+ Other small bug fixes.
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* 1.4
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+ Added support for `frintm`.
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+ Fixed simulation of `frintn` and `frinta` for corner cases.
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+ Added more tests for floating point instruction simulation.
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+ Modified `CalleeSave()` and `CalleeRestore()` to push general purpose
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registers before floating point registers on the stack.
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+ Fixed Printf for mixed argument types, and use on real hardware.
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+ Improved compatibility with some 32-bit compilers.
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* 1.3
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+ Address inaccuracies in the simulated floating point instructions.
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+ Implement Default-NaN floating point mode.
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+ Introduce `UseScratchRegisterScope` for controlling the use of temporary
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registers.
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+ Enable building VIXL on 32-bit hosts.
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+ Other small bug fixes and improvements.
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* 1.2
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+ Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,
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`frinta`, `fcvtau` and `fcvtas`.
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+ Added support for assembling and disassembling `isb`, `dsb` and `dmb`.
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+ Added support for automatic inversion of compare instructions when using
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negative immediates.
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+ Added support for using `movn` when generating immediates.
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+ Added explicit flag-setting 'S' instructions, and removed
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`SetFlags` and `LeaveFlags` arguments.
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+ Added support for `Movk` in macro assembler.
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+ Added support for W register parameters to `Tbz` and `Tbnz`.
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+ Added support for using immediate operands with `Csel`.
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+ Added new debugger syntax for memory inspection.
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+ Fixed `smull`, `fmsub` and `sdiv` simulation.
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+ Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`.
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+ Prevented code generation for certain side-effect free operations,
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such as `add r, r, #0`, in the macro assembler.
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+ Other small bug fixes.
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* 1.1
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+ Improved robustness of instruction decoder and disassembler.
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+ Added support for double-to-float conversions using `fcvt`.
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+ Added support for more fixed-point to floating-point conversions (`ucvtf`
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and `scvtf`).
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+ Added instruction statistics collection class `instrument-a64.cc`.
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* 1.0
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+ Initial release.
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