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110 lines
3.1 KiB
110 lines
3.1 KiB
// Copyright 2016, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Test description for instructions of the following form:
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// MNEMONIC{<c>}.W <Rd>, #<imm16>
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{
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"mnemonics" : [
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"Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
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"Movt", // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
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"Movw" // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3
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],
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"description" : {
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"operands": [
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{
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"name": "cond",
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"type": "Condition"
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},
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{
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"name": "rd",
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"type": "AllRegistersButPC"
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},
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{
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"name": "op",
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"wrapper": "Operand",
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"operands": [
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{
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"name": "immediate",
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"type": "Imm16"
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}
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]
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}
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],
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"inputs": [
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{
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"name": "apsr",
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"type": "NZCV"
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},
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{
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"name": "rd",
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"type": "Register"
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}
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]
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},
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"test-files": [
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{
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"type": "assembler",
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"test-cases": [
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{
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"name": "Operands",
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"operands": [
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"cond", "rd", "immediate"
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],
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"operand-filter": "cond == 'al'"
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}
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]
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},
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{
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"type": "simulator",
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"mnemonics" : [
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"Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
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"Movt" // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
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],
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"test-cases": [
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{
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"name": "Condition",
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"operands": [
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"cond"
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],
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"inputs": [
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"apsr"
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]
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},
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{
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"name": "ModifiedImmediate",
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"operands": [
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"immediate"
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],
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"inputs": [
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"rd"
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]
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}
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]
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}
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]
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}
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