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314 lines
9.5 KiB
314 lines
9.5 KiB
// Copyright 2016, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Test description for instructions with the following operands:
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// MNEMONIC<c> <rd>, <rn>, <rm>
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//
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// The instructions covered in this test do not write to the `Q` and `GE` flags,
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// these are covered in other description files.
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{
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"mnemonics": [
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"Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
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"Muls", // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
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"Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shadd8", // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shasx", // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shsax", // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shsub16", // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Shsub8", // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smmul", // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smmulr", // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smuad", // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smuadx", // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smulbb", // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smulbt", // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smultb", // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smultt", // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smulwb", // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smulwt", // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smusd", // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Smusdx", // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Udiv", // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhadd16", // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhadd8", // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhasx", // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhsax", // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhsub16", // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uhsub8", // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqadd16", // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqadd8", // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqasx", // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqsax", // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqsub16", // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uqsub8", // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Usad8", // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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// Instructions affecting the GE bits.
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"Sadd16", // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Sadd8", // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Sasx", // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Sel", // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Ssax", // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Ssub16", // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Ssub8", // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uadd16", // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uadd8", // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Uasx", // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Usax", // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Usub16", // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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"Usub8", // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
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// Instructions affecting the Q bit.
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"Qadd", // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
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"Qdadd", // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
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"Qdsub", // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
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"Qsub" // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
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],
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"description": {
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"operands": [
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{
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"name": "cond",
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"type": "Condition"
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},
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{
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"name": "rd",
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"type": "AllRegistersButPC"
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},
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{
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"name": "rn",
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"type": "AllRegistersButPC"
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},
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{
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"name": "rm",
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"type": "AllRegistersButPC"
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}
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],
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"inputs": [
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{
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"name": "apsr",
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"type": "NZCV"
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},
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{
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"name": "qbit",
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"type": "Q"
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},
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{
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"name": "ge",
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"type": "GE"
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},
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{
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"name": "rd",
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"type": "Register"
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},
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{
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"name": "rn",
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"type": "Register"
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},
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{
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"name": "rm",
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"type": "Register"
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}
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]
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},
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"test-files": [
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{
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"type": "assembler",
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"test-cases": [
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{
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"name": "Operands",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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"operand-limit": 300
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}
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]
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},
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{
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"type": "simulator",
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"test-cases": [
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{
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"name": "Condition",
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"operands": [
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"cond"
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],
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"inputs": [
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"apsr"
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]
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},
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{
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"name": "RdIsRnIsRm",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"rd", "rn", "rm"
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],
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"operand-filter": "(rd == rn) and (rd == rm)",
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"input-filter": "(rd == rn) and (rd == rm)"
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},
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{
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"name": "RdIsRn",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"rd", "rn", "rm"
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],
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"operand-filter": "(rd == rn) and (rn != rm)",
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"operand-limit": 10,
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"input-filter": "rd == rn",
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"input-limit": 200
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},
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{
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"name": "RdIsRm",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"rd", "rn", "rm"
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],
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"operand-filter": "(rd == rm) and (rn != rm)",
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"operand-limit": 10,
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"input-filter": "rd == rm",
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"input-limit": 200
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},
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{
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"name": "RnIsRm",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"rd", "rn", "rm"
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],
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"operand-filter": "(rn == rm) and (rm != rd)",
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"operand-limit": 10,
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"input-filter": "rn == rm",
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"input-limit": 200
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},
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{
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"name": "RdIsNotRnIsNotRm",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"rd", "rn", "rm"
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],
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"operand-filter": "(rd != rn) and (rd != rm)",
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"operand-limit": 10,
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"input-limit": 200
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}
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]
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},
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{
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"name": "ge",
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"type": "simulator",
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"mnemonics": [
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"Sadd16",
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"Sadd8",
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"Sasx",
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"Ssax",
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"Ssub16",
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"Ssub8",
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"Uadd16",
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"Uadd8",
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"Uasx",
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"Usax",
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"Usub16",
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"Usub8"
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],
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"test-cases": [
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{
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"name": "GE",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"ge", "rn", "rm"
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],
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"operand-filter": "(rd != rn) and (rn != rm)",
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"operand-limit": 1,
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// Only use "all set" and "all cleared" as inputs.
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"input-filter": "ge == 'NoFlag' or ge == 'GE0123Flag'",
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"input-limit": 200
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}
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]
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},
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{
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"name": "sel",
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"type": "simulator",
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"mnemonics": [
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"Sel"
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],
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"test-cases": [
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{
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"name": "GE",
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"operands": [
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"rd", "rn", "rm"
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],
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"inputs": [
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"ge", "rn", "rm"
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],
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"operand-filter": "(rd != rn) and (rn != rm)",
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"operand-limit": 1,
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"input-limit": 200
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}
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]
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},
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{
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"name": "q",
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"type": "simulator",
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"mnemonics": [
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"Qadd",
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"Qdadd",
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"Qdsub",
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"Qsub"
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],
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"test-cases": [
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{
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"name": "QOutput",
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"operands": [
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"rn", "rm"
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],
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"inputs": [
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"qbit", "rn", "rm"
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],
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"operand-limit": 1,
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"operand-filter": "rn != rm",
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"input-limit": 200
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}
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]
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}
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]
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}
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