You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
314 lines
9.5 KiB
314 lines
9.5 KiB
// Copyright 2016, VIXL authors
|
|
// All rights reserved.
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without
|
|
// modification, are permitted provided that the following conditions are met:
|
|
//
|
|
// * Redistributions of source code must retain the above copyright notice,
|
|
// this list of conditions and the following disclaimer.
|
|
// * Redistributions in binary form must reproduce the above copyright notice,
|
|
// this list of conditions and the following disclaimer in the documentation
|
|
// and/or other materials provided with the distribution.
|
|
// * Neither the name of ARM Limited nor the names of its contributors may be
|
|
// used to endorse or promote products derived from this software without
|
|
// specific prior written permission.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
|
|
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
// Test description for instructions of the following form:
|
|
// MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
|
|
//
|
|
// The instructions covered in this test do not write to the `Q` and `GE` flags,
|
|
// these are covered in other description files.
|
|
|
|
{
|
|
"mnemonics": [
|
|
"Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2
|
|
"Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shadd8", // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shasx", // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shsax", // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shsub16", // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Shsub8", // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smmul", // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smmulr", // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smuad", // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smuadx", // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smulbb", // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smulbt", // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smultb", // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smultt", // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smulwb", // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smulwt", // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smusd", // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Smusdx", // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Udiv", // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhadd16", // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhadd8", // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhasx", // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhsax", // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhsub16", // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uhsub8", // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqadd16", // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqadd8", // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqasx", // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqsax", // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqsub16", // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uqsub8", // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Usad8", // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
|
|
// Instructions affecting the GE bits.
|
|
"Sadd16", // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Sadd8", // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Sasx", // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Sel", // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Ssax", // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Ssub16", // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Ssub8", // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uadd16", // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uadd8", // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Uasx", // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Usax", // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Usub16", // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
"Usub8", // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
|
|
|
// Instructions affecting the Q bit.
|
|
"Qadd", // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
|
|
"Qdadd", // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
|
|
"Qdsub", // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
|
|
"Qsub" // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
|
|
],
|
|
"description": {
|
|
"operands": [
|
|
{
|
|
"name": "cond",
|
|
"type": "Condition"
|
|
},
|
|
{
|
|
"name": "rd",
|
|
"type": "AllRegistersButPC"
|
|
},
|
|
{
|
|
"name": "rn",
|
|
"type": "AllRegistersButPC"
|
|
},
|
|
{
|
|
"name": "rm",
|
|
"type": "AllRegistersButPC"
|
|
}
|
|
],
|
|
"inputs": [
|
|
{
|
|
"name": "apsr",
|
|
"type": "NZCV"
|
|
},
|
|
{
|
|
"name": "qbit",
|
|
"type": "Q"
|
|
},
|
|
{
|
|
"name": "ge",
|
|
"type": "GE"
|
|
},
|
|
{
|
|
"name": "rd",
|
|
"type": "Register"
|
|
},
|
|
{
|
|
"name": "rn",
|
|
"type": "Register"
|
|
},
|
|
{
|
|
"name": "rm",
|
|
"type": "Register"
|
|
}
|
|
]
|
|
},
|
|
"test-files": [
|
|
{
|
|
"type": "assembler",
|
|
"test-cases": [
|
|
{
|
|
"name": "Unconditional",
|
|
"operands": [
|
|
"cond", "rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "cond == 'al'",
|
|
"operand-limit": 300
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"type": "simulator",
|
|
"test-cases": [
|
|
{
|
|
"name": "Condition",
|
|
"operands": [
|
|
"cond"
|
|
],
|
|
"inputs": [
|
|
"apsr"
|
|
]
|
|
},
|
|
{
|
|
"name": "RdIsRnIsRm",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd == rn) and (rd == rm)",
|
|
"input-filter": "(rd == rn) and (rd == rm)"
|
|
},
|
|
{
|
|
"name": "RdIsRn",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd == rn) and (rn != rm)",
|
|
"operand-limit": 10,
|
|
"input-filter": "rd == rn",
|
|
"input-limit": 200
|
|
},
|
|
{
|
|
"name": "RdIsRm",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd == rm) and (rn != rm)",
|
|
"operand-limit": 10,
|
|
"input-filter": "rd == rm",
|
|
"input-limit": 200
|
|
},
|
|
{
|
|
"name": "RnIsRm",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rn == rm) and (rm != rd)",
|
|
"operand-limit": 10,
|
|
"input-filter": "rn == rm",
|
|
"input-limit": 200
|
|
},
|
|
{
|
|
"name": "RdIsNotRnIsNotRm",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd != rn) and (rd != rm)",
|
|
"operand-limit": 10,
|
|
"input-limit": 200
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "ge",
|
|
"type": "simulator",
|
|
"mnemonics": [
|
|
"Sadd16",
|
|
"Sadd8",
|
|
"Sasx",
|
|
"Ssax",
|
|
"Ssub16",
|
|
"Ssub8",
|
|
"Uadd16",
|
|
"Uadd8",
|
|
"Uasx",
|
|
"Usax",
|
|
"Usub16",
|
|
"Usub8"
|
|
],
|
|
"test-cases": [
|
|
{
|
|
"name": "GE",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"ge", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd != rn) and (rn != rm)",
|
|
"operand-limit": 1,
|
|
// Only use "all set" and "all cleared" as inputs.
|
|
"input-filter": "ge == 'NoFlag' or ge == 'GE0123Flag'",
|
|
"input-limit": 200
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "sel",
|
|
"type": "simulator",
|
|
"mnemonics": [
|
|
"Sel"
|
|
],
|
|
"test-cases": [
|
|
{
|
|
"name": "GE",
|
|
"operands": [
|
|
"rd", "rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"ge", "rn", "rm"
|
|
],
|
|
"operand-filter": "(rd != rn) and (rn != rm)",
|
|
"operand-limit": 1,
|
|
"input-limit": 200
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "q",
|
|
"type": "simulator",
|
|
"mnemonics": [
|
|
"Qadd",
|
|
"Qdadd",
|
|
"Qdsub",
|
|
"Qsub"
|
|
],
|
|
"test-cases": [
|
|
{
|
|
"name": "QOutput",
|
|
"operands": [
|
|
"rn", "rm"
|
|
],
|
|
"inputs": [
|
|
"qbit", "rn", "rm"
|
|
],
|
|
"operand-limit": 1,
|
|
"operand-filter": "rn != rm",
|
|
"input-limit": 200
|
|
}
|
|
]
|
|
}
|
|
]
|
|
}
|