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1084 lines
52 KiB
1084 lines
52 KiB
// Copyright 2016, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// -----------------------------------------------------------------------------
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// This file is auto generated from the
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// test/aarch32/config/template-simulator-aarch32.cc.in template file using
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// tools/generate_tests.py.
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//
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// PLEASE DO NOT EDIT.
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// -----------------------------------------------------------------------------
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#include "test-runner.h"
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#include "test-utils.h"
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#include "test-utils-aarch32.h"
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#include "aarch32/assembler-aarch32.h"
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#include "aarch32/disasm-aarch32.h"
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#include "aarch32/macro-assembler-aarch32.h"
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#define __ masm.
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#define BUF_SIZE (4096)
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#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
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// Run tests with the simulator.
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#define SETUP() MacroAssembler masm(BUF_SIZE)
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#define START() masm.GetBuffer()->Reset()
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#define END() \
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__ Hlt(0); \
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__ FinalizeCode();
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// TODO: Run the tests in the simulator.
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#define RUN()
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#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
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#define SETUP() \
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MacroAssembler masm(BUF_SIZE); \
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UseScratchRegisterScope harness_scratch;
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#define START() \
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harness_scratch.Open(&masm); \
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harness_scratch.ExcludeAll(); \
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masm.GetBuffer()->Reset(); \
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__ Push(r4); \
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__ Push(r5); \
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__ Push(r6); \
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__ Push(r7); \
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__ Push(r8); \
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__ Push(r9); \
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__ Push(r10); \
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__ Push(r11); \
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__ Push(lr); \
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harness_scratch.Include(ip);
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#define END() \
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harness_scratch.Exclude(ip); \
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__ Pop(lr); \
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__ Pop(r11); \
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__ Pop(r10); \
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__ Pop(r9); \
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__ Pop(r8); \
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__ Pop(r7); \
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__ Pop(r6); \
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__ Pop(r5); \
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__ Pop(r4); \
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__ Bx(lr); \
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__ FinalizeCode(); \
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harness_scratch.Close();
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#define RUN() \
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{ \
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int pcs_offset = masm.IsUsingT32() ? 1 : 0; \
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masm.GetBuffer()->SetExecutable(); \
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ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \
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masm.GetSizeOfCodeGenerated(), \
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pcs_offset); \
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masm.GetBuffer()->SetWritable(); \
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}
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#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
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namespace vixl {
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namespace aarch32 {
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// List of instruction encodings:
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#define FOREACH_INSTRUCTION(M) \
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M(Cmn) \
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M(Cmp) \
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M(Mov) \
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M(Movs) \
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M(Mvn) \
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M(Mvns) \
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M(Teq) \
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M(Tst)
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// The following definitions are defined again in each generated test, therefore
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// we need to place them in an anomymous namespace. It expresses that they are
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// local to this file only, and the compiler is not allowed to share these types
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// across test files during template instantiation. Specifically, `Operands` and
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// `Inputs` have various layouts across generated tests so they absolutely
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// cannot be shared.
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#ifdef VIXL_INCLUDE_TARGET_T32
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namespace {
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// Values to be passed to the assembler to produce the instruction under test.
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struct Operands {
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Condition cond;
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Register rd;
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Register rn;
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ShiftType shift;
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uint32_t amount;
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};
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// Input data to feed to the instruction.
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struct Inputs {
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uint32_t apsr;
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uint32_t rd;
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uint32_t rn;
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};
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// This structure contains all input data needed to test one specific encoding.
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// It used to generate a loop over an instruction.
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struct TestLoopData {
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// The `operands` fields represents the values to pass to the assembler to
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// produce the instruction.
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Operands operands;
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// Description of the operands, used for error reporting.
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const char* operands_description;
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// Unique identifier, used for generating traces.
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const char* identifier;
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// Array of values to be fed to the instruction.
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size_t input_size;
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const Inputs* inputs;
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};
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static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab},
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{ZFlag, 0xabababab, 0xabababab},
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{CFlag, 0xabababab, 0xabababab},
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{VFlag, 0xabababab, 0xabababab},
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{NZFlag, 0xabababab, 0xabababab},
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{NCFlag, 0xabababab, 0xabababab},
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{NVFlag, 0xabababab, 0xabababab},
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{ZCFlag, 0xabababab, 0xabababab},
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{ZVFlag, 0xabababab, 0xabababab},
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{CVFlag, 0xabababab, 0xabababab},
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{NZCFlag, 0xabababab, 0xabababab},
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{NZVFlag, 0xabababab, 0xabababab},
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{NCVFlag, 0xabababab, 0xabababab},
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{ZCVFlag, 0xabababab, 0xabababab},
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{NZCVFlag, 0xabababab, 0xabababab}};
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static const Inputs kRdIsRn[] =
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{{NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x00000001, 0x00000001},
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{NoFlag, 0x00000002, 0x00000002}, {NoFlag, 0x00000020, 0x00000020},
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{NoFlag, 0x0000007d, 0x0000007d}, {NoFlag, 0x0000007e, 0x0000007e},
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{NoFlag, 0x0000007f, 0x0000007f}, {NoFlag, 0x00007ffd, 0x00007ffd},
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{NoFlag, 0x00007ffe, 0x00007ffe}, {NoFlag, 0x00007fff, 0x00007fff},
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{NoFlag, 0x33333333, 0x33333333}, {NoFlag, 0x55555555, 0x55555555},
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{NoFlag, 0x7ffffffd, 0x7ffffffd}, {NoFlag, 0x7ffffffe, 0x7ffffffe},
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{NoFlag, 0x7fffffff, 0x7fffffff}, {NoFlag, 0x80000000, 0x80000000},
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{NoFlag, 0x80000001, 0x80000001}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
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{NoFlag, 0xcccccccc, 0xcccccccc}, {NoFlag, 0xffff8000, 0xffff8000},
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{NoFlag, 0xffff8001, 0xffff8001}, {NoFlag, 0xffff8002, 0xffff8002},
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{NoFlag, 0xffff8003, 0xffff8003}, {NoFlag, 0xffffff80, 0xffffff80},
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{NoFlag, 0xffffff81, 0xffffff81}, {NoFlag, 0xffffff82, 0xffffff82},
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{NoFlag, 0xffffff83, 0xffffff83}, {NoFlag, 0xffffffe0, 0xffffffe0},
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{NoFlag, 0xfffffffd, 0xfffffffd}, {NoFlag, 0xfffffffe, 0xfffffffe},
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{NoFlag, 0xffffffff, 0xffffffff}};
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static const Inputs kRdIsNotRn[] =
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{{NoFlag, 0x00000002, 0xcccccccc}, {NoFlag, 0x7ffffffd, 0x00007ffe},
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{NoFlag, 0xffffff80, 0x00000020}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
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{NoFlag, 0x33333333, 0xffffff82}, {NoFlag, 0xffff8001, 0x7ffffffe},
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{NoFlag, 0xfffffffd, 0x00007ffe}, {NoFlag, 0xffffff80, 0x80000000},
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{NoFlag, 0x00000001, 0x33333333}, {NoFlag, 0xcccccccc, 0x7ffffffe},
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{NoFlag, 0x00000000, 0xcccccccc}, {NoFlag, 0x00000000, 0x55555555},
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{NoFlag, 0xffffffff, 0xffffffff}, {NoFlag, 0x0000007e, 0xffff8002},
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{NoFlag, 0x80000000, 0x7ffffffd}, {NoFlag, 0xffffff81, 0x0000007e},
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{NoFlag, 0x0000007f, 0xffff8001}, {NoFlag, 0xffffffe0, 0x00007ffd},
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{NoFlag, 0xffff8003, 0x00000002}, {NoFlag, 0xffffff83, 0x55555555},
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{NoFlag, 0xffffff83, 0xffffff80}, {NoFlag, 0xffffff81, 0xffff8000},
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{NoFlag, 0x00000020, 0x7ffffffe}, {NoFlag, 0xffffffe0, 0x00000000},
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{NoFlag, 0x7fffffff, 0x0000007e}, {NoFlag, 0x80000001, 0xffffffff},
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{NoFlag, 0x00000001, 0x80000001}, {NoFlag, 0x00000002, 0x0000007f},
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{NoFlag, 0x7fffffff, 0xcccccccc}, {NoFlag, 0x80000001, 0x00007ffe},
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{NoFlag, 0xffff8002, 0x0000007e}, {NoFlag, 0x00007ffe, 0xcccccccc},
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{NoFlag, 0x80000000, 0xffff8002}, {NoFlag, 0xffffff83, 0x7ffffffe},
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{NoFlag, 0xffff8001, 0x00000001}, {NoFlag, 0xffffff81, 0x00000020},
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{NoFlag, 0xfffffffe, 0xffff8001}, {NoFlag, 0xffffffff, 0xfffffffe},
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{NoFlag, 0xcccccccc, 0x55555555}, {NoFlag, 0x00000020, 0xffffff83},
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{NoFlag, 0xffffff83, 0xffff8001}, {NoFlag, 0xffffff83, 0xffff8000},
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{NoFlag, 0x00007fff, 0x00000002}, {NoFlag, 0x55555555, 0xffff8000},
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{NoFlag, 0x80000001, 0xffffff81}, {NoFlag, 0x00000002, 0x00000000},
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{NoFlag, 0x33333333, 0xffffff81}, {NoFlag, 0xffff8001, 0xffffff82},
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{NoFlag, 0xcccccccc, 0xffff8003}, {NoFlag, 0xffff8003, 0x7ffffffd},
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{NoFlag, 0x0000007d, 0x00007ffe}, {NoFlag, 0xffffff80, 0x0000007d},
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{NoFlag, 0xaaaaaaaa, 0x00007ffd}, {NoFlag, 0x80000000, 0xffffff82},
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{NoFlag, 0x00000002, 0x7ffffffe}, {NoFlag, 0x00000002, 0xffffff83},
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{NoFlag, 0x55555555, 0x00000002}, {NoFlag, 0xffffffff, 0xffffff82},
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{NoFlag, 0xaaaaaaaa, 0x00000020}, {NoFlag, 0x00000001, 0xffffff82},
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{NoFlag, 0x0000007f, 0xffffff82}, {NoFlag, 0x7ffffffd, 0xaaaaaaaa},
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{NoFlag, 0x00007ffe, 0x00000001}, {NoFlag, 0xfffffffd, 0xffffffe0},
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{NoFlag, 0xffffff81, 0xffffff83}, {NoFlag, 0x0000007d, 0x00000000},
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{NoFlag, 0x0000007d, 0xffff8000}, {NoFlag, 0xffffff81, 0x7fffffff},
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{NoFlag, 0xffffffff, 0x80000000}, {NoFlag, 0x00000000, 0x00000001},
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{NoFlag, 0x55555555, 0xffffff82}, {NoFlag, 0x00007ffe, 0x00007ffe},
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{NoFlag, 0x80000001, 0xfffffffd}, {NoFlag, 0x00007fff, 0x33333333},
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{NoFlag, 0x00007fff, 0x80000000}, {NoFlag, 0xcccccccc, 0x00007fff},
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{NoFlag, 0xfffffffe, 0xffffffe0}, {NoFlag, 0x7ffffffe, 0x0000007f},
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{NoFlag, 0x00007ffd, 0xffff8001}, {NoFlag, 0x00000002, 0x00000001},
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{NoFlag, 0x80000000, 0xffffffff}, {NoFlag, 0xffffff83, 0xcccccccc},
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{NoFlag, 0xffff8002, 0x7ffffffe}, {NoFlag, 0xaaaaaaaa, 0x00000000},
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{NoFlag, 0xffffff80, 0xcccccccc}, {NoFlag, 0x33333333, 0xffffff83},
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{NoFlag, 0x0000007e, 0xffffffe0}, {NoFlag, 0x0000007e, 0x00007fff},
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{NoFlag, 0x0000007f, 0x00000002}, {NoFlag, 0x7ffffffe, 0xcccccccc},
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{NoFlag, 0x0000007d, 0xffffff80}, {NoFlag, 0x00007fff, 0x00000020},
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{NoFlag, 0x7ffffffe, 0xfffffffe}, {NoFlag, 0xfffffffe, 0xffffff81},
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{NoFlag, 0xffffffff, 0x0000007f}, {NoFlag, 0xffff8002, 0x7ffffffd},
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{NoFlag, 0xffff8001, 0xfffffffe}, {NoFlag, 0x33333333, 0xffff8002},
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{NoFlag, 0x00000000, 0xffffffff}, {NoFlag, 0x33333333, 0xffffff80},
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{NoFlag, 0x0000007f, 0x00007fff}, {NoFlag, 0xffffffff, 0xffff8001},
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{NoFlag, 0x7fffffff, 0xffff8002}, {NoFlag, 0x7ffffffd, 0xffffff83},
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{NoFlag, 0x7fffffff, 0x0000007f}, {NoFlag, 0xffffff83, 0xfffffffe},
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{NoFlag, 0x7ffffffe, 0xffff8003}, {NoFlag, 0xffff8002, 0xffff8002},
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{NoFlag, 0x80000001, 0x0000007f}, {NoFlag, 0x00000020, 0x00000002},
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{NoFlag, 0xffffff82, 0xffff8001}, {NoFlag, 0xffffffff, 0x00000001},
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{NoFlag, 0xffffff80, 0xffff8002}, {NoFlag, 0xffff8003, 0x7fffffff},
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{NoFlag, 0xffffffff, 0xffff8000}, {NoFlag, 0xffff8002, 0x00007ffd},
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{NoFlag, 0x00000020, 0xffffff81}, {NoFlag, 0x00000001, 0x55555555},
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{NoFlag, 0x7ffffffe, 0x00000020}, {NoFlag, 0x80000000, 0x00000001},
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{NoFlag, 0x00007ffd, 0xffff8002}, {NoFlag, 0x7fffffff, 0xfffffffe},
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{NoFlag, 0xcccccccc, 0x00007ffd}, {NoFlag, 0x00000000, 0xfffffffd},
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{NoFlag, 0xffff8003, 0xffffff80}, {NoFlag, 0x80000001, 0xffffff80},
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{NoFlag, 0xffffffff, 0xffff8002}, {NoFlag, 0x00007ffe, 0xffff8002},
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{NoFlag, 0xffffff80, 0x00007ffe}, {NoFlag, 0x80000001, 0xffff8001},
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{NoFlag, 0x0000007f, 0xffffff80}, {NoFlag, 0xffffff81, 0x80000000},
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{NoFlag, 0x00007fff, 0x00007ffe}, {NoFlag, 0x33333333, 0xffff8000},
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{NoFlag, 0x33333333, 0x00007fff}, {NoFlag, 0x00000000, 0x0000007d},
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{NoFlag, 0x80000001, 0x00000000}, {NoFlag, 0xffffffff, 0x55555555},
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{NoFlag, 0x80000001, 0x80000000}, {NoFlag, 0xffffffff, 0xffffff80},
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{NoFlag, 0xffffff81, 0xffff8003}, {NoFlag, 0x55555555, 0x80000001},
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{NoFlag, 0x7fffffff, 0xffff8001}, {NoFlag, 0xffffff83, 0x00000002},
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{NoFlag, 0x0000007e, 0xffffff81}, {NoFlag, 0x80000000, 0xffff8001},
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{NoFlag, 0xffffff80, 0xfffffffe}, {NoFlag, 0x0000007e, 0xfffffffd},
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{NoFlag, 0xffffffe0, 0xffffffff}, {NoFlag, 0x55555555, 0x80000000},
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{NoFlag, 0x0000007d, 0x80000001}, {NoFlag, 0xffffffe0, 0x7ffffffd},
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{NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x55555555, 0x00000001},
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{NoFlag, 0x00007ffd, 0x7fffffff}, {NoFlag, 0x55555555, 0xffffffff},
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{NoFlag, 0xffff8003, 0x00007fff}, {NoFlag, 0xffffff82, 0x00007fff},
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{NoFlag, 0x33333333, 0x55555555}, {NoFlag, 0x00000020, 0x33333333},
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{NoFlag, 0x7ffffffe, 0xfffffffd}, {NoFlag, 0x7ffffffe, 0x00000001},
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{NoFlag, 0xffffff83, 0xffffffe0}, {NoFlag, 0xfffffffe, 0xaaaaaaaa},
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{NoFlag, 0xffff8002, 0x33333333}, {NoFlag, 0xffff8002, 0xffff8003},
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{NoFlag, 0x33333333, 0x7fffffff}, {NoFlag, 0xfffffffd, 0xffffff83},
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{NoFlag, 0x00000000, 0xffff8000}, {NoFlag, 0xffffff82, 0x55555555},
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{NoFlag, 0xffffff82, 0xffffff81}, {NoFlag, 0xcccccccc, 0xfffffffe},
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{NoFlag, 0xfffffffd, 0x7fffffff}, {NoFlag, 0x00007fff, 0x7fffffff},
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{NoFlag, 0xffffff83, 0xffff8003}, {NoFlag, 0xfffffffe, 0xffffffff},
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{NoFlag, 0x7ffffffd, 0x00007ffd}, {NoFlag, 0x7ffffffd, 0x00007fff},
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{NoFlag, 0x00007ffd, 0xffffffff}, {NoFlag, 0x00000001, 0xffff8003},
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{NoFlag, 0xffffff80, 0xfffffffd}, {NoFlag, 0x33333333, 0x80000000},
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{NoFlag, 0xffff8001, 0x00000020}, {NoFlag, 0xcccccccc, 0x00000002},
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{NoFlag, 0x00000000, 0x00000002}, {NoFlag, 0x0000007d, 0x00007fff},
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{NoFlag, 0xcccccccc, 0x00000001}, {NoFlag, 0xffffff83, 0x00007fff},
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{NoFlag, 0x80000001, 0x00000020}, {NoFlag, 0xffff8003, 0xffffffe0},
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{NoFlag, 0x00007ffd, 0xaaaaaaaa}, {NoFlag, 0x33333333, 0xffff8001},
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{NoFlag, 0xffffff83, 0x80000001}, {NoFlag, 0xffff8000, 0xffff8000},
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{NoFlag, 0x00007ffe, 0xffff8001}, {NoFlag, 0x7ffffffd, 0x00000000},
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{NoFlag, 0x00007ffe, 0x33333333}, {NoFlag, 0xffff8001, 0xffffff80},
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{NoFlag, 0xfffffffe, 0x55555555}, {NoFlag, 0xffffff82, 0xffffffff}};
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static const Inputs kShiftTypes[] =
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{{NoFlag, 0xabababab, 0x00000000}, {NoFlag, 0xabababab, 0x00000001},
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{NoFlag, 0xabababab, 0x00000002}, {NoFlag, 0xabababab, 0x00000020},
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{NoFlag, 0xabababab, 0x0000007d}, {NoFlag, 0xabababab, 0x0000007e},
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{NoFlag, 0xabababab, 0x0000007f}, {NoFlag, 0xabababab, 0x00007ffd},
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{NoFlag, 0xabababab, 0x00007ffe}, {NoFlag, 0xabababab, 0x00007fff},
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{NoFlag, 0xabababab, 0x33333333}, {NoFlag, 0xabababab, 0x55555555},
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{NoFlag, 0xabababab, 0x7ffffffd}, {NoFlag, 0xabababab, 0x7ffffffe},
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{NoFlag, 0xabababab, 0x7fffffff}, {NoFlag, 0xabababab, 0x80000000},
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{NoFlag, 0xabababab, 0x80000001}, {NoFlag, 0xabababab, 0xaaaaaaaa},
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{NoFlag, 0xabababab, 0xcccccccc}, {NoFlag, 0xabababab, 0xffff8000},
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{NoFlag, 0xabababab, 0xffff8001}, {NoFlag, 0xabababab, 0xffff8002},
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{NoFlag, 0xabababab, 0xffff8003}, {NoFlag, 0xabababab, 0xffffff80},
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{NoFlag, 0xabababab, 0xffffff81}, {NoFlag, 0xabababab, 0xffffff82},
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{NoFlag, 0xabababab, 0xffffff83}, {NoFlag, 0xabababab, 0xffffffe0},
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{NoFlag, 0xabababab, 0xfffffffd}, {NoFlag, 0xabababab, 0xfffffffe},
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{NoFlag, 0xabababab, 0xffffffff}};
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// A loop will be generated for each element of this array.
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const TestLoopData kTests[] = {{{eq, r0, r0, LSR, 1},
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"eq r0 r0 LSR 1",
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"Condition_eq_r0_r0_LSR_1",
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ARRAY_SIZE(kCondition),
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kCondition},
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{{ne, r0, r0, LSR, 1},
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"ne r0 r0 LSR 1",
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"Condition_ne_r0_r0_LSR_1",
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ARRAY_SIZE(kCondition),
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kCondition},
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{{cs, r0, r0, LSR, 1},
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"cs r0 r0 LSR 1",
|
|
"Condition_cs_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{cc, r0, r0, LSR, 1},
|
|
"cc r0 r0 LSR 1",
|
|
"Condition_cc_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{mi, r0, r0, LSR, 1},
|
|
"mi r0 r0 LSR 1",
|
|
"Condition_mi_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{pl, r0, r0, LSR, 1},
|
|
"pl r0 r0 LSR 1",
|
|
"Condition_pl_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{vs, r0, r0, LSR, 1},
|
|
"vs r0 r0 LSR 1",
|
|
"Condition_vs_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{vc, r0, r0, LSR, 1},
|
|
"vc r0 r0 LSR 1",
|
|
"Condition_vc_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{hi, r0, r0, LSR, 1},
|
|
"hi r0 r0 LSR 1",
|
|
"Condition_hi_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{ls, r0, r0, LSR, 1},
|
|
"ls r0 r0 LSR 1",
|
|
"Condition_ls_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{ge, r0, r0, LSR, 1},
|
|
"ge r0 r0 LSR 1",
|
|
"Condition_ge_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{lt, r0, r0, LSR, 1},
|
|
"lt r0 r0 LSR 1",
|
|
"Condition_lt_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{gt, r0, r0, LSR, 1},
|
|
"gt r0 r0 LSR 1",
|
|
"Condition_gt_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{le, r0, r0, LSR, 1},
|
|
"le r0 r0 LSR 1",
|
|
"Condition_le_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{al, r0, r0, LSR, 1},
|
|
"al r0 r0 LSR 1",
|
|
"Condition_al_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kCondition),
|
|
kCondition},
|
|
{{al, r0, r0, LSR, 1},
|
|
"al r0 r0 LSR 1",
|
|
"RdIsRn_al_r0_r0_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r1, r1, LSR, 1},
|
|
"al r1 r1 LSR 1",
|
|
"RdIsRn_al_r1_r1_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r2, r2, LSR, 1},
|
|
"al r2 r2 LSR 1",
|
|
"RdIsRn_al_r2_r2_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r3, r3, LSR, 1},
|
|
"al r3 r3 LSR 1",
|
|
"RdIsRn_al_r3_r3_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r4, r4, LSR, 1},
|
|
"al r4 r4 LSR 1",
|
|
"RdIsRn_al_r4_r4_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r5, r5, LSR, 1},
|
|
"al r5 r5 LSR 1",
|
|
"RdIsRn_al_r5_r5_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r6, r6, LSR, 1},
|
|
"al r6 r6 LSR 1",
|
|
"RdIsRn_al_r6_r6_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r7, r7, LSR, 1},
|
|
"al r7 r7 LSR 1",
|
|
"RdIsRn_al_r7_r7_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r8, r8, LSR, 1},
|
|
"al r8 r8 LSR 1",
|
|
"RdIsRn_al_r8_r8_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r9, r9, LSR, 1},
|
|
"al r9 r9 LSR 1",
|
|
"RdIsRn_al_r9_r9_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r10, r10, LSR, 1},
|
|
"al r10 r10 LSR 1",
|
|
"RdIsRn_al_r10_r10_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r11, r11, LSR, 1},
|
|
"al r11 r11 LSR 1",
|
|
"RdIsRn_al_r11_r11_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r12, r12, LSR, 1},
|
|
"al r12 r12 LSR 1",
|
|
"RdIsRn_al_r12_r12_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r14, r14, LSR, 1},
|
|
"al r14 r14 LSR 1",
|
|
"RdIsRn_al_r14_r14_LSR_1",
|
|
ARRAY_SIZE(kRdIsRn),
|
|
kRdIsRn},
|
|
{{al, r1, r8, LSR, 1},
|
|
"al r1 r8 LSR 1",
|
|
"RdIsNotRn_al_r1_r8_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r7, r4, LSR, 1},
|
|
"al r7 r4 LSR 1",
|
|
"RdIsNotRn_al_r7_r4_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r14, r10, LSR, 1},
|
|
"al r14 r10 LSR 1",
|
|
"RdIsNotRn_al_r14_r10_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r10, r6, LSR, 1},
|
|
"al r10 r6 LSR 1",
|
|
"RdIsNotRn_al_r10_r6_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r6, r5, LSR, 1},
|
|
"al r6 r5 LSR 1",
|
|
"RdIsNotRn_al_r6_r5_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r12, r2, LSR, 1},
|
|
"al r12 r2 LSR 1",
|
|
"RdIsNotRn_al_r12_r2_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r0, r11, LSR, 1},
|
|
"al r0 r11 LSR 1",
|
|
"RdIsNotRn_al_r0_r11_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r10, r14, LSR, 1},
|
|
"al r10 r14 LSR 1",
|
|
"RdIsNotRn_al_r10_r14_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r0, r5, LSR, 1},
|
|
"al r0 r5 LSR 1",
|
|
"RdIsNotRn_al_r0_r5_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r0, r3, LSR, 1},
|
|
"al r0 r3 LSR 1",
|
|
"RdIsNotRn_al_r0_r3_LSR_1",
|
|
ARRAY_SIZE(kRdIsNotRn),
|
|
kRdIsNotRn},
|
|
{{al, r0, r1, LSR, 1},
|
|
"al r0 r1 LSR 1",
|
|
"ShiftTypes_al_r0_r1_LSR_1",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 2},
|
|
"al r0 r1 LSR 2",
|
|
"ShiftTypes_al_r0_r1_LSR_2",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 3},
|
|
"al r0 r1 LSR 3",
|
|
"ShiftTypes_al_r0_r1_LSR_3",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 4},
|
|
"al r0 r1 LSR 4",
|
|
"ShiftTypes_al_r0_r1_LSR_4",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 5},
|
|
"al r0 r1 LSR 5",
|
|
"ShiftTypes_al_r0_r1_LSR_5",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 6},
|
|
"al r0 r1 LSR 6",
|
|
"ShiftTypes_al_r0_r1_LSR_6",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 7},
|
|
"al r0 r1 LSR 7",
|
|
"ShiftTypes_al_r0_r1_LSR_7",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 8},
|
|
"al r0 r1 LSR 8",
|
|
"ShiftTypes_al_r0_r1_LSR_8",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 9},
|
|
"al r0 r1 LSR 9",
|
|
"ShiftTypes_al_r0_r1_LSR_9",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 10},
|
|
"al r0 r1 LSR 10",
|
|
"ShiftTypes_al_r0_r1_LSR_10",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 11},
|
|
"al r0 r1 LSR 11",
|
|
"ShiftTypes_al_r0_r1_LSR_11",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 12},
|
|
"al r0 r1 LSR 12",
|
|
"ShiftTypes_al_r0_r1_LSR_12",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 13},
|
|
"al r0 r1 LSR 13",
|
|
"ShiftTypes_al_r0_r1_LSR_13",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 14},
|
|
"al r0 r1 LSR 14",
|
|
"ShiftTypes_al_r0_r1_LSR_14",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 15},
|
|
"al r0 r1 LSR 15",
|
|
"ShiftTypes_al_r0_r1_LSR_15",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 16},
|
|
"al r0 r1 LSR 16",
|
|
"ShiftTypes_al_r0_r1_LSR_16",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 17},
|
|
"al r0 r1 LSR 17",
|
|
"ShiftTypes_al_r0_r1_LSR_17",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 18},
|
|
"al r0 r1 LSR 18",
|
|
"ShiftTypes_al_r0_r1_LSR_18",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 19},
|
|
"al r0 r1 LSR 19",
|
|
"ShiftTypes_al_r0_r1_LSR_19",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 20},
|
|
"al r0 r1 LSR 20",
|
|
"ShiftTypes_al_r0_r1_LSR_20",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 21},
|
|
"al r0 r1 LSR 21",
|
|
"ShiftTypes_al_r0_r1_LSR_21",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 22},
|
|
"al r0 r1 LSR 22",
|
|
"ShiftTypes_al_r0_r1_LSR_22",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 23},
|
|
"al r0 r1 LSR 23",
|
|
"ShiftTypes_al_r0_r1_LSR_23",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 24},
|
|
"al r0 r1 LSR 24",
|
|
"ShiftTypes_al_r0_r1_LSR_24",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 25},
|
|
"al r0 r1 LSR 25",
|
|
"ShiftTypes_al_r0_r1_LSR_25",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 26},
|
|
"al r0 r1 LSR 26",
|
|
"ShiftTypes_al_r0_r1_LSR_26",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 27},
|
|
"al r0 r1 LSR 27",
|
|
"ShiftTypes_al_r0_r1_LSR_27",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 28},
|
|
"al r0 r1 LSR 28",
|
|
"ShiftTypes_al_r0_r1_LSR_28",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 29},
|
|
"al r0 r1 LSR 29",
|
|
"ShiftTypes_al_r0_r1_LSR_29",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 30},
|
|
"al r0 r1 LSR 30",
|
|
"ShiftTypes_al_r0_r1_LSR_30",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 31},
|
|
"al r0 r1 LSR 31",
|
|
"ShiftTypes_al_r0_r1_LSR_31",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, LSR, 32},
|
|
"al r0 r1 LSR 32",
|
|
"ShiftTypes_al_r0_r1_LSR_32",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 1},
|
|
"al r0 r1 ASR 1",
|
|
"ShiftTypes_al_r0_r1_ASR_1",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 2},
|
|
"al r0 r1 ASR 2",
|
|
"ShiftTypes_al_r0_r1_ASR_2",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 3},
|
|
"al r0 r1 ASR 3",
|
|
"ShiftTypes_al_r0_r1_ASR_3",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 4},
|
|
"al r0 r1 ASR 4",
|
|
"ShiftTypes_al_r0_r1_ASR_4",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 5},
|
|
"al r0 r1 ASR 5",
|
|
"ShiftTypes_al_r0_r1_ASR_5",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 6},
|
|
"al r0 r1 ASR 6",
|
|
"ShiftTypes_al_r0_r1_ASR_6",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 7},
|
|
"al r0 r1 ASR 7",
|
|
"ShiftTypes_al_r0_r1_ASR_7",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 8},
|
|
"al r0 r1 ASR 8",
|
|
"ShiftTypes_al_r0_r1_ASR_8",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 9},
|
|
"al r0 r1 ASR 9",
|
|
"ShiftTypes_al_r0_r1_ASR_9",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 10},
|
|
"al r0 r1 ASR 10",
|
|
"ShiftTypes_al_r0_r1_ASR_10",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 11},
|
|
"al r0 r1 ASR 11",
|
|
"ShiftTypes_al_r0_r1_ASR_11",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 12},
|
|
"al r0 r1 ASR 12",
|
|
"ShiftTypes_al_r0_r1_ASR_12",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 13},
|
|
"al r0 r1 ASR 13",
|
|
"ShiftTypes_al_r0_r1_ASR_13",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 14},
|
|
"al r0 r1 ASR 14",
|
|
"ShiftTypes_al_r0_r1_ASR_14",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 15},
|
|
"al r0 r1 ASR 15",
|
|
"ShiftTypes_al_r0_r1_ASR_15",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 16},
|
|
"al r0 r1 ASR 16",
|
|
"ShiftTypes_al_r0_r1_ASR_16",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 17},
|
|
"al r0 r1 ASR 17",
|
|
"ShiftTypes_al_r0_r1_ASR_17",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 18},
|
|
"al r0 r1 ASR 18",
|
|
"ShiftTypes_al_r0_r1_ASR_18",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 19},
|
|
"al r0 r1 ASR 19",
|
|
"ShiftTypes_al_r0_r1_ASR_19",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 20},
|
|
"al r0 r1 ASR 20",
|
|
"ShiftTypes_al_r0_r1_ASR_20",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 21},
|
|
"al r0 r1 ASR 21",
|
|
"ShiftTypes_al_r0_r1_ASR_21",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 22},
|
|
"al r0 r1 ASR 22",
|
|
"ShiftTypes_al_r0_r1_ASR_22",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 23},
|
|
"al r0 r1 ASR 23",
|
|
"ShiftTypes_al_r0_r1_ASR_23",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 24},
|
|
"al r0 r1 ASR 24",
|
|
"ShiftTypes_al_r0_r1_ASR_24",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 25},
|
|
"al r0 r1 ASR 25",
|
|
"ShiftTypes_al_r0_r1_ASR_25",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 26},
|
|
"al r0 r1 ASR 26",
|
|
"ShiftTypes_al_r0_r1_ASR_26",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 27},
|
|
"al r0 r1 ASR 27",
|
|
"ShiftTypes_al_r0_r1_ASR_27",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 28},
|
|
"al r0 r1 ASR 28",
|
|
"ShiftTypes_al_r0_r1_ASR_28",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 29},
|
|
"al r0 r1 ASR 29",
|
|
"ShiftTypes_al_r0_r1_ASR_29",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 30},
|
|
"al r0 r1 ASR 30",
|
|
"ShiftTypes_al_r0_r1_ASR_30",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 31},
|
|
"al r0 r1 ASR 31",
|
|
"ShiftTypes_al_r0_r1_ASR_31",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes},
|
|
{{al, r0, r1, ASR, 32},
|
|
"al r0 r1 ASR 32",
|
|
"ShiftTypes_al_r0_r1_ASR_32",
|
|
ARRAY_SIZE(kShiftTypes),
|
|
kShiftTypes}};
|
|
|
|
// We record all inputs to the instructions as outputs. This way, we also check
|
|
// that what shouldn't change didn't change.
|
|
struct TestResult {
|
|
size_t output_size;
|
|
const Inputs* outputs;
|
|
};
|
|
|
|
// These headers each contain an array of `TestResult` with the reference output
|
|
// values. The reference arrays are names `kReference{mnemonic}`.
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-cmn-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-cmp-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mov-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-movs-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mvn-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mvns-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-teq-t32.h"
|
|
#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-tst-t32.h"
|
|
|
|
|
|
// The maximum number of errors to report in detail for each test.
|
|
const unsigned kErrorReportLimit = 8;
|
|
|
|
typedef void (MacroAssembler::*Fn)(Condition cond,
|
|
Register rd,
|
|
const Operand& op);
|
|
|
|
void TestHelper(Fn instruction,
|
|
const char* mnemonic,
|
|
const TestResult reference[]) {
|
|
SETUP();
|
|
masm.UseT32();
|
|
START();
|
|
|
|
// Data to compare to `reference`.
|
|
TestResult* results[ARRAY_SIZE(kTests)];
|
|
|
|
// Test cases for memory bound instructions may allocate a buffer and save its
|
|
// address in this array.
|
|
byte* scratch_memory_buffers[ARRAY_SIZE(kTests)];
|
|
|
|
// Generate a loop for each element in `kTests`. Each loop tests one specific
|
|
// instruction.
|
|
for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
|
|
// Allocate results on the heap for this test.
|
|
results[i] = new TestResult;
|
|
results[i]->outputs = new Inputs[kTests[i].input_size];
|
|
results[i]->output_size = kTests[i].input_size;
|
|
|
|
size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size;
|
|
VIXL_ASSERT(IsUint32(input_stride));
|
|
|
|
scratch_memory_buffers[i] = NULL;
|
|
|
|
Label loop;
|
|
UseScratchRegisterScope scratch_registers(&masm);
|
|
// Include all registers from r0 ro r12.
|
|
scratch_registers.Include(RegisterList(0x1fff));
|
|
|
|
// Values to pass to the macro-assembler.
|
|
Condition cond = kTests[i].operands.cond;
|
|
Register rd = kTests[i].operands.rd;
|
|
Register rn = kTests[i].operands.rn;
|
|
ShiftType shift = kTests[i].operands.shift;
|
|
uint32_t amount = kTests[i].operands.amount;
|
|
Operand op(rn, shift, amount);
|
|
scratch_registers.Exclude(rd);
|
|
scratch_registers.Exclude(rn);
|
|
|
|
// Allocate reserved registers for our own use.
|
|
Register input_ptr = scratch_registers.Acquire();
|
|
Register input_end = scratch_registers.Acquire();
|
|
Register result_ptr = scratch_registers.Acquire();
|
|
|
|
// Initialize `input_ptr` to the first element and `input_end` the address
|
|
// after the array.
|
|
__ Mov(input_ptr, Operand::From(kTests[i].inputs));
|
|
__ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride));
|
|
__ Mov(result_ptr, Operand::From(results[i]->outputs));
|
|
__ Bind(&loop);
|
|
|
|
{
|
|
UseScratchRegisterScope temp_registers(&masm);
|
|
Register nzcv_bits = temp_registers.Acquire();
|
|
Register saved_q_bit = temp_registers.Acquire();
|
|
// Save the `Q` bit flag.
|
|
__ Mrs(saved_q_bit, APSR);
|
|
__ And(saved_q_bit, saved_q_bit, QFlag);
|
|
// Set the `NZCV` and `Q` flags together.
|
|
__ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
|
|
__ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
|
|
__ Msr(APSR_nzcvq, nzcv_bits);
|
|
}
|
|
__ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
|
|
__ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
|
|
|
|
(masm.*instruction)(cond, rd, op);
|
|
|
|
{
|
|
UseScratchRegisterScope temp_registers(&masm);
|
|
Register nzcv_bits = temp_registers.Acquire();
|
|
__ Mrs(nzcv_bits, APSR);
|
|
// Only record the NZCV bits.
|
|
__ And(nzcv_bits, nzcv_bits, NZCVFlag);
|
|
__ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr)));
|
|
}
|
|
__ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd)));
|
|
__ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn)));
|
|
|
|
// Advance the result pointer.
|
|
__ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
|
|
// Loop back until `input_ptr` is lower than `input_base`.
|
|
__ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
|
|
__ Cmp(input_ptr, input_end);
|
|
__ B(ne, &loop);
|
|
}
|
|
|
|
END();
|
|
|
|
RUN();
|
|
|
|
if (Test::generate_test_trace()) {
|
|
// Print the results.
|
|
for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
|
|
printf("const Inputs kOutputs_%s_%s[] = {\n",
|
|
mnemonic,
|
|
kTests[i].identifier);
|
|
for (size_t j = 0; j < results[i]->output_size; j++) {
|
|
printf(" { ");
|
|
printf("0x%08" PRIx32, results[i]->outputs[j].apsr);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, results[i]->outputs[j].rd);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, results[i]->outputs[j].rn);
|
|
printf(" },\n");
|
|
}
|
|
printf("};\n");
|
|
}
|
|
printf("const TestResult kReference%s[] = {\n", mnemonic);
|
|
for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
|
|
printf(" {\n");
|
|
printf(" ARRAY_SIZE(kOutputs_%s_%s),\n",
|
|
mnemonic,
|
|
kTests[i].identifier);
|
|
printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier);
|
|
printf(" },\n");
|
|
}
|
|
printf("};\n");
|
|
} else if (kCheckSimulatorTestResults) {
|
|
// Check the results.
|
|
unsigned total_error_count = 0;
|
|
for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
|
|
bool instruction_has_errors = false;
|
|
for (size_t j = 0; j < kTests[i].input_size; j++) {
|
|
uint32_t apsr = results[i]->outputs[j].apsr;
|
|
uint32_t rd = results[i]->outputs[j].rd;
|
|
uint32_t rn = results[i]->outputs[j].rn;
|
|
uint32_t apsr_input = kTests[i].inputs[j].apsr;
|
|
uint32_t rd_input = kTests[i].inputs[j].rd;
|
|
uint32_t rn_input = kTests[i].inputs[j].rn;
|
|
uint32_t apsr_ref = reference[i].outputs[j].apsr;
|
|
uint32_t rd_ref = reference[i].outputs[j].rd;
|
|
uint32_t rn_ref = reference[i].outputs[j].rn;
|
|
|
|
if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) &&
|
|
(++total_error_count <= kErrorReportLimit)) {
|
|
// Print the instruction once even if it triggered multiple failures.
|
|
if (!instruction_has_errors) {
|
|
printf("Error(s) when testing \"%s %s\":\n",
|
|
mnemonic,
|
|
kTests[i].operands_description);
|
|
instruction_has_errors = true;
|
|
}
|
|
// Print subsequent errors.
|
|
printf(" Input: ");
|
|
printf("0x%08" PRIx32, apsr_input);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rd_input);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rn_input);
|
|
printf("\n");
|
|
printf(" Expected: ");
|
|
printf("0x%08" PRIx32, apsr_ref);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rd_ref);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rn_ref);
|
|
printf("\n");
|
|
printf(" Found: ");
|
|
printf("0x%08" PRIx32, apsr);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rd);
|
|
printf(", ");
|
|
printf("0x%08" PRIx32, rn);
|
|
printf("\n\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
if (total_error_count > kErrorReportLimit) {
|
|
printf("%u other errors follow.\n",
|
|
total_error_count - kErrorReportLimit);
|
|
}
|
|
VIXL_CHECK(total_error_count == 0);
|
|
} else {
|
|
VIXL_WARNING("Assembled the code, but did not run anything.\n");
|
|
}
|
|
|
|
for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
|
|
delete[] results[i]->outputs;
|
|
delete results[i];
|
|
delete[] scratch_memory_buffers[i];
|
|
}
|
|
}
|
|
|
|
// Instantiate tests for each instruction in the list.
|
|
// TODO: Remove this limitation by having a sandboxing mechanism.
|
|
#if defined(VIXL_HOST_POINTER_32)
|
|
#define TEST(mnemonic) \
|
|
void Test_##mnemonic() { \
|
|
TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
|
|
} \
|
|
Test test_##mnemonic( \
|
|
"AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" #mnemonic \
|
|
"_T32", \
|
|
&Test_##mnemonic);
|
|
#else
|
|
#define TEST(mnemonic) \
|
|
void Test_##mnemonic() { \
|
|
VIXL_WARNING("This test can only run on a 32-bit host.\n"); \
|
|
USE(TestHelper); \
|
|
} \
|
|
Test test_##mnemonic( \
|
|
"AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" #mnemonic \
|
|
"_T32", \
|
|
&Test_##mnemonic);
|
|
#endif
|
|
|
|
FOREACH_INSTRUCTION(TEST)
|
|
#undef TEST
|
|
|
|
} // namespace
|
|
#endif
|
|
|
|
} // namespace aarch32
|
|
} // namespace vixl
|