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263 lines
8.0 KiB
263 lines
8.0 KiB
// Copyright 2015, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "aarch32/test-utils-aarch32.h"
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#define __ masm->
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namespace vixl {
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namespace aarch32 {
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#define VIXL_OFFSET(type, member) offsetof(type, member)
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void RegisterDump::Dump(MacroAssembler* masm) {
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UseScratchRegisterScope scratch(masm);
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scratch.ExcludeAll();
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// Preserve some temporary registers.
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Register dump_base = r0;
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Register tmp = r1;
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// Check that the the dump registers can be used
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VIXL_STATIC_ASSERT(sizeof(dump_.r_[0]) == kRegSizeInBytes);
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VIXL_STATIC_ASSERT(sizeof(dump_.d_[0]) == kDRegSizeInBytes);
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// Offsets into the dump_ structure.
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const int r_offset = static_cast<int>(VIXL_OFFSET(dump_t, r_));
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const int d_offset = static_cast<int>(VIXL_OFFSET(dump_t, d_));
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const int flags_offset = static_cast<int>(VIXL_OFFSET(dump_t, flags_));
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__ Push(dump_base);
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__ Push(tmp);
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// Load the address of the dump_ structure.
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__ Mov(dump_base, Operand::From(&dump_));
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// Dump all core registers. Note that the stack pointer and temporary
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// registers will be stored again later after they are restored.
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for (unsigned i = 0; i < kNumberOfRegisters; i++) {
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Register rt(i);
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// In T32 mode, "str pc, [base, #offset]" is not allowed so we cannot store
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// the program counter this way. We could however compute the relative
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// offset from the start of the buffer and store it but it's not very
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// useful. So for now, testing the value of the PC is not supported.
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if (!rt.IsPC()) {
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__ Str(rt, MemOperand(dump_base, r_offset + (i * kRegSizeInBytes)));
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}
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}
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for (unsigned i = 0; i < kMaxNumberOfDRegisters; i++) {
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DRegister rt(i);
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__ Vstr(Untyped64,
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rt,
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MemOperand(dump_base, d_offset + (i * kDRegSizeInBytes)));
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}
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// Dump the flags.
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__ Mrs(tmp, APSR);
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__ Str(tmp, MemOperand(dump_base, flags_offset));
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// We need a new pointer to dump_ in order to dump the temporary registers and
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// the stack pointer.
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Register dump2_base = r2;
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// TODO: Assert that dump_base, dump2_base and tmp are not aliases.
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__ Mov(dump2_base, dump_base);
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__ Pop(tmp);
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__ Pop(dump_base);
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// Dump tmp, dump_base and the stack pointer.
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__ Str(tmp,
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MemOperand(dump2_base, r_offset + (tmp.GetCode() * kRegSizeInBytes)));
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__ Str(dump_base,
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MemOperand(dump2_base,
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r_offset + (dump_base.GetCode() * kRegSizeInBytes)));
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__ Str(sp, MemOperand(dump2_base, r_offset + (kSPRegNum * kRegSizeInBytes)));
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completed_ = true;
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}
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bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result) {
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if (result != expected) {
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printf("Expected 0x%08" PRIx32 "\t Found 0x%08" PRIx32 "\n",
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expected,
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result);
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}
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return expected == result;
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}
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bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
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if (reg.IsPC()) {
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printf("Testing the value of the program counter is not supported.");
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return false;
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} else {
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return Equal32(expected, core, core->reg(reg.GetCode()));
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}
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}
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bool Equal32(uint32_t expected,
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const RegisterDump* core,
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const SRegister& sreg) {
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return Equal32(expected, core, core->GetSRegisterBits(sreg.GetCode()));
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}
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bool Equal64(uint64_t expected, const RegisterDump*, uint64_t result) {
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if (result != expected) {
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printf("Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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expected,
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result);
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}
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return expected == result;
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}
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bool Equal64(uint64_t expected,
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const RegisterDump* core,
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const DRegister& dreg) {
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return Equal64(expected, core, core->GetDRegisterBits(dreg.GetCode()));
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}
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bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
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if ((result.h != expected.h) || (result.l != expected.l)) {
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printf("Expected 0x%016" PRIx64 "%016" PRIx64
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"\t "
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"Found 0x%016" PRIx64 "%016" PRIx64 "\n",
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expected.h,
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expected.l,
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result.h,
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result.l);
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}
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return ((expected.h == result.h) && (expected.l == result.l));
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}
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bool Equal128(uint64_t expected_h,
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uint64_t expected_l,
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const RegisterDump* core,
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const QRegister& qreg) {
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vec128_t expected = {expected_l, expected_h};
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vec128_t result = core->GetQRegisterBits(qreg.GetCode());
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return Equal128(expected, core, result);
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}
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static char FlagN(uint32_t flags) { return (flags & NFlag) ? 'N' : 'n'; }
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static char FlagZ(uint32_t flags) { return (flags & ZFlag) ? 'Z' : 'z'; }
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static char FlagC(uint32_t flags) { return (flags & CFlag) ? 'C' : 'c'; }
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static char FlagV(uint32_t flags) { return (flags & VFlag) ? 'V' : 'v'; }
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bool EqualNzcv(uint32_t expected, uint32_t result) {
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VIXL_ASSERT((expected & ~NZCVFlag) == 0);
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VIXL_ASSERT((result & ~NZCVFlag) == 0);
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if (result != expected) {
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printf("Expected: %c%c%c%c\t Found: %c%c%c%c\n",
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FlagN(expected),
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FlagZ(expected),
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FlagC(expected),
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FlagV(expected),
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FlagN(result),
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FlagZ(result),
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FlagC(result),
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FlagV(result));
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return false;
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}
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return true;
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}
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bool EqualFP32(float expected,
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const RegisterDump* core,
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const SRegister& sreg) {
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// Retrieve the corresponding S register
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uint32_t result = core->GetSRegisterBits(sreg.GetCode());
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if (FloatToRawbits(expected) == result) {
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return true;
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} else {
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if (IsNaN(expected) || (expected == 0.0)) {
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printf("Expected 0x%08" PRIx32 "\t Found 0x%08" PRIx32 "\n",
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FloatToRawbits(expected),
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result);
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} else {
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printf("Expected %.9f (0x%08" PRIx32
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")\t "
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"Found %.9f (0x%08" PRIx32 ")\n",
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expected,
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FloatToRawbits(expected),
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RawbitsToFloat(result),
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result);
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}
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return false;
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}
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}
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bool EqualFP64(double expected,
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const RegisterDump* core,
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const DRegister& dreg) {
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// Retrieve the corresponding D register
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uint64_t result = core->GetDRegisterBits(dreg.GetCode());
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if (DoubleToRawbits(expected) == result) {
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return true;
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}
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if (IsNaN(expected) || (expected == 0.0)) {
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printf("Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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DoubleToRawbits(expected),
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DoubleToRawbits(result));
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} else {
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printf("Expected %.17f (0x%016" PRIx64
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")\t "
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"Found %.17f (0x%016" PRIx64 ")\n",
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expected,
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DoubleToRawbits(expected),
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RawbitsToDouble(result),
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result);
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}
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return false;
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}
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} // namespace aarch32
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} // namespace vixl
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