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206 lines
7.1 KiB
206 lines
7.1 KiB
// Copyright 2017, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_AARCH32_TEST_UTILS_AARCH32_H_
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#define VIXL_AARCH32_TEST_UTILS_AARCH32_H_
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#include "../test-pool-manager.h"
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#include "../test-runner.h"
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#include "aarch32/constants-aarch32.h"
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#include "aarch32/instructions-aarch32.h"
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#include "aarch32/macro-assembler-aarch32.h"
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namespace vixl {
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namespace aarch32 {
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class TestMacroAssembler {
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public:
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explicit TestMacroAssembler(MacroAssembler* masm)
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: test(&masm->pool_manager_) {}
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int32_t GetPoolCheckpoint() const { return test.GetPoolCheckpoint(); }
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int GetPoolSize() const { return test.GetPoolSize(); }
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bool PoolIsEmpty() const { return test.PoolIsEmpty(); }
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private:
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TestPoolManager test;
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};
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// Only check the simulator tests when we can actually run them.
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// TODO: Improve this.
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#if defined(__arm__)
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static const bool kCheckSimulatorTestResults = true;
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#else
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static const bool kCheckSimulatorTestResults = false;
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#endif
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// Helper constants used to check for condition code combinations. These are
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// not part of instruction definitions as no instruction uses them directly.
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const uint32_t NoFlag = 0x0;
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const uint32_t NFlag = 0x80000000;
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const uint32_t ZFlag = 0x40000000;
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const uint32_t CFlag = 0x20000000;
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const uint32_t VFlag = 0x10000000;
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const uint32_t NZFlag = NFlag | ZFlag;
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const uint32_t NCFlag = NFlag | CFlag;
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const uint32_t NVFlag = NFlag | VFlag;
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const uint32_t ZCFlag = ZFlag | CFlag;
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const uint32_t ZVFlag = ZFlag | VFlag;
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const uint32_t CVFlag = CFlag | VFlag;
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const uint32_t NZCFlag = NFlag | ZFlag | CFlag;
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const uint32_t NZVFlag = NFlag | ZFlag | VFlag;
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const uint32_t NCVFlag = NFlag | CFlag | VFlag;
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const uint32_t ZCVFlag = ZFlag | CFlag | VFlag;
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const uint32_t NZCVFlag = NFlag | ZFlag | CFlag | VFlag;
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const uint32_t QFlag = 0x08000000;
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const uint32_t GE0Flag = 0x00010000;
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const uint32_t GE1Flag = 0x00020000;
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const uint32_t GE2Flag = 0x00040000;
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const uint32_t GE3Flag = 0x00080000;
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const uint32_t GE01Flag = GE0Flag | GE1Flag;
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const uint32_t GE02Flag = GE0Flag | GE2Flag;
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const uint32_t GE03Flag = GE0Flag | GE3Flag;
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const uint32_t GE12Flag = GE1Flag | GE2Flag;
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const uint32_t GE13Flag = GE1Flag | GE3Flag;
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const uint32_t GE23Flag = GE2Flag | GE3Flag;
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const uint32_t GE012Flag = GE0Flag | GE1Flag | GE2Flag;
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const uint32_t GE013Flag = GE0Flag | GE1Flag | GE3Flag;
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const uint32_t GE023Flag = GE0Flag | GE2Flag | GE3Flag;
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const uint32_t GE123Flag = GE1Flag | GE2Flag | GE3Flag;
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const uint32_t GE0123Flag = GE0Flag | GE1Flag | GE2Flag | GE3Flag;
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const uint32_t GEFlags = GE0123Flag;
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struct vec128_t {
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uint64_t l;
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uint64_t h;
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};
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class RegisterDump {
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public:
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RegisterDump() : completed_(false) {
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VIXL_ASSERT(sizeof(dump_.r_[0]) == kRegSizeInBytes);
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}
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// The Dump method generates code to store a snapshot of the register values.
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// It needs to be able to use the stack temporarily.
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//
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// The dumping code is generated though the given MacroAssembler. No registers
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// are corrupted in the process apart for the program counter, but the stack
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// is used briefly. Note the program counter cannot be retrieved from the
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// register dump anyway.
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void Dump(MacroAssembler* masm);
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// Register accessors.
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int32_t reg(unsigned code) const {
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VIXL_ASSERT(IsComplete());
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// The collected program counter should not be accessed.
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VIXL_ASSERT(code != kPcCode);
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return dump_.r_[code];
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}
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// QRegister accessors
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vec128_t GetQRegisterBits(unsigned code) const {
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VIXL_ASSERT(IsComplete());
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VIXL_ASSERT(code < kNumberOfQRegisters);
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vec128_t content = {dump_.d_[code * 2], dump_.d_[(code * 2) + 1]};
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return content;
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}
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// DRegister accessors
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uint64_t GetDRegisterBits(unsigned code) const {
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VIXL_ASSERT(IsComplete());
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VIXL_ASSERT(code < kMaxNumberOfDRegisters);
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return dump_.d_[code];
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}
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// SRegister accessors
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uint32_t GetSRegisterBits(unsigned code) const {
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VIXL_ASSERT(IsComplete());
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VIXL_ASSERT(code < kNumberOfSRegisters);
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if ((code % 2) == 0) {
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return GetDRegisterBits(code / 2) & 0xffffffff;
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} else {
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return GetDRegisterBits(code / 2) >> 32;
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}
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VIXL_UNREACHABLE();
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return 0;
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}
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// Stack pointer accessors.
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int32_t spreg() const { return reg(kSPRegNum); }
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// Flags accessors.
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uint32_t flags_nzcv() const {
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VIXL_ASSERT(IsComplete());
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return dump_.flags_ & NZCVFlag;
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}
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bool IsComplete() const { return completed_; }
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private:
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// Indicate whether the dump operation has been completed.
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bool completed_;
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// Store all the dumped elements in a simple struct so the implementation can
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// use offsetof to quickly find the correct field.
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struct dump_t {
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// Core registers, except for PC.
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uint32_t r_[kNumberOfRegisters - 1];
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uint64_t d_[kMaxNumberOfDRegisters];
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// NZCV flags, stored in bits 28 to 31.
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// bit[31] : Negative
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// bit[30] : Zero
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// bit[29] : Carry
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// bit[28] : oVerflow
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uint32_t flags_;
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} dump_;
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};
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bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg);
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bool Equal32(uint32_t expected, const RegisterDump* core, uint32_t result);
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bool Equal32(uint32_t expected,
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const RegisterDump* core,
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const SRegister& sreg);
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bool Equal64(uint64_t expected,
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const RegisterDump* core,
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const DRegister& dreg);
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bool Equal128(uint64_t expected_h,
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uint64_t expected_l,
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const RegisterDump* core,
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const QRegister& qreg);
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bool EqualFP32(float expected, const RegisterDump* core, const SRegister& dreg);
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bool EqualFP64(double expected,
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const RegisterDump* core,
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const DRegister& dreg);
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bool EqualNzcv(uint32_t expected, uint32_t result);
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} // namespace aarch32
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} // namespace vixl
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#endif // VIXL_AARCH32_TEST_UTILS_AARCH32_H_
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