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v811_spc009/external/vixl/test/aarch64/traces/sim-fcvtas-xd-trace-aarch64.h

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// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of ARM Limited nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------
#ifndef VIXL_SIM_FCVTAS_XD_TRACE_AARCH64_H_
#define VIXL_SIM_FCVTAS_XD_TRACE_AARCH64_H_
const int64_t kExpected_fcvtas_xd[] = {
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(2),
INT64_C(10),
INT64_C(9223372036854775807),
INT64_C(9223372036854775807),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(9223372036854775807),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(2),
-INT64_C(10),
-INT64_C(9223372036854775807) - 1,
-INT64_C(9223372036854775807) - 1,
INT64_C(0),
INT64_C(0),
INT64_C(0),
-INT64_C(9223372036854775807) - 1,
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(9223372036854775807),
INT64_C(0),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(1),
INT64_C(9223372036854775807),
INT64_C(9223372036854775807),
INT64_C(9223372036854775807),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
-INT64_C(9223372036854775807) - 1,
INT64_C(0),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(1),
-INT64_C(9223372036854775807) - 1,
-INT64_C(9223372036854775807) - 1,
-INT64_C(9223372036854775807) - 1,
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(0),
INT64_C(4503599627370496),
INT64_C(4503599627370497),
INT64_C(4503599627370498),
INT64_C(4503599627370499),
INT64_C(8987183256397123),
INT64_C(9007199254740988),
INT64_C(9007199254740989),
INT64_C(9007199254740990),
INT64_C(9007199254740991),
INT64_C(2251799813685248),
INT64_C(2251799813685249),
INT64_C(2251799813685249),
INT64_C(2251799813685250),
INT64_C(4493591628198562),
INT64_C(4503599627370494),
INT64_C(4503599627370495),
INT64_C(4503599627370495),
INT64_C(4503599627370496),
INT64_C(1125899906842624),
INT64_C(1125899906842624),
INT64_C(1125899906842625),
INT64_C(1125899906842625),
INT64_C(2246795814099281),
INT64_C(2251799813685247),
INT64_C(2251799813685247),
INT64_C(2251799813685248),
INT64_C(2251799813685248),
-INT64_C(4503599627370496),
-INT64_C(4503599627370497),
-INT64_C(4503599627370498),
-INT64_C(4503599627370499),
-INT64_C(8987183256397123),
-INT64_C(9007199254740988),
-INT64_C(9007199254740989),
-INT64_C(9007199254740990),
-INT64_C(9007199254740991),
-INT64_C(2251799813685248),
-INT64_C(2251799813685249),
-INT64_C(2251799813685249),
-INT64_C(2251799813685250),
-INT64_C(4493591628198562),
-INT64_C(4503599627370494),
-INT64_C(4503599627370495),
-INT64_C(4503599627370495),
-INT64_C(4503599627370496),
-INT64_C(1125899906842624),
-INT64_C(1125899906842624),
-INT64_C(1125899906842625),
-INT64_C(1125899906842625),
-INT64_C(2246795814099281),
-INT64_C(2251799813685247),
-INT64_C(2251799813685247),
-INT64_C(2251799813685248),
-INT64_C(2251799813685248),
-INT64_C(9223372036854775807) - 1,
-INT64_C(9223372036854775807) - 1,
-INT64_C(9223372036854774784),
INT64_C(9223372036854774784),
INT64_C(9223372036854775807),
INT64_C(9223372036854775807),
INT64_C(9223372036854775807),
-INT64_C(2147483649),
-INT64_C(2147483649),
-INT64_C(2147483649),
-INT64_C(2147483649),
-INT64_C(2147483649),
-INT64_C(2147483648),
-INT64_C(2147483648),
-INT64_C(2147483648),
-INT64_C(2147483648),
-INT64_C(2147483648),
-INT64_C(2147483648),
-INT64_C(2147483647),
INT64_C(2147483646),
INT64_C(2147483646),
INT64_C(2147483646),
INT64_C(2147483646),
INT64_C(2147483647),
INT64_C(2147483647),
INT64_C(2147483647),
INT64_C(2147483647),
INT64_C(2147483647),
INT64_C(2147483647),
INT64_C(2147483648),
INT64_C(2147483648),
INT64_C(4294967294),
INT64_C(4294967294),
INT64_C(4294967294),
INT64_C(4294967294),
INT64_C(4294967295),
INT64_C(4294967295),
INT64_C(4294967295),
INT64_C(4294967295),
INT64_C(4294967295),
INT64_C(4294967295),
INT64_C(4294967296),
INT64_C(4294967296),
};
const unsigned kExpectedCount_fcvtas_xd = 207;
#endif // VIXL_SIM_FCVTAS_XD_TRACE_AARCH64_H_
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