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v811_spc009/vendor/huanglong/linux/drv/frontend/drv_frontend.h

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/*
* Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2021. All rights reserved.
* Description: frontend
* Author: Hisilicon
* Created: 2017-06-30
*/
#ifndef __DRV_FRONTEND_H__
#define __DRV_FRONTEND_H__
#include "soc_log.h"
#include "soc_errno.h"
#include "drv_ioctl_frontend.h"
#include "drv_i2c_ext.h"
#include "drv_gpioi2c_ext.h"
#include "drv_gpio_ext.h"
#include "osal_ext.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
#undef LOG_MODULE_ID
#define LOG_MODULE_ID SOC_ID_FRONTEND
#define TIME_CONSUMING 0
#if TIME_CONSUMING
#define time_cost_define(lable) osal_timeval st_start_time##lable, st_end_time##lable
#define time_cost_start(lable) osal_gettimeofday(&st_start_time##lable)
#define time_cost_end(lable, msg) do { \
long total; \
osal_gettimeofday(&st_end_time##lable); \
total = (st_end_time##lable.tv_sec - st_start_time##lable.tv_sec) * 1000 \
+ (st_end_time##lable.tv_usec - st_start_time##lable.tv_usec) / 1000; \
soc_log_warn(msg " cost %dms.\n", total); \
} while (0)
#else
#define time_cost_define(lable)
#define time_cost_start(lable)
#define time_cost_end(lable, msg)
#endif
#define soc_warn_print_reg8(reg, val) soc_log_warn("%s : %02x\n", #reg, val)
#define soc_info_print_reg8(reg, val) soc_log_info("%s : %02x\n", #reg, val)
#define soc_dbg_print_reg8(reg, val) soc_log_dbg("%s : %02x\n", #reg, val)
#define fe_check_param(val, err_code_print, err_code_ret) do { \
if (val) { \
soc_err_print_err_code(err_code_print); \
return err_code_ret; \
} \
} while (0)
#define fe_check(func) do { \
td_s32 err_code_ = func; \
if (err_code_ != TD_SUCCESS) { \
soc_warn_print_call_fun_err(#func, err_code_); \
} \
} while (0)
#define drv_fe_check_pointer(p) \
fe_check_param(((p) == TD_NULL), SOC_ERR_FRONTEND_INVALID_POINT, SOC_ERR_FRONTEND_INVALID_POINT)
#define drv_fe_check_func_pointer(pfn) \
fe_check_param(((pfn) == TD_NULL), SOC_ERR_FRONTEND_INVALID_POINT, SOC_ERR_FRONTEND_INVALID_POINT)
#define drv_fe_ctrl_check_is_dtv_c(sig_type) \
fe_check_param(((sig_type) < EXT_DRV_FRONTEND_SIG_TYPE_DVB_C || (sig_type) > EXT_DRV_FRONTEND_SIG_TYPE_J83B), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_is_dtv_t(sig_type) \
fe_check_param(((sig_type) < EXT_DRV_FRONTEND_SIG_TYPE_DVB_T || (sig_type) > EXT_DRV_FRONTEND_SIG_TYPE_DTMB), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_is_dtv_s(sig_type) \
fe_check_param(((sig_type) < EXT_DRV_FRONTEND_SIG_TYPE_DVB_S || (sig_type) > EXT_DRV_FRONTEND_SIG_TYPE_ABSS), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_port(port) \
fe_check_param(((port) >= DRV_FRONTEND_NUM), SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_tuner_type(tuner_type) \
fe_check_param(((tuner_type) >= EXT_DRV_TUNER_DEV_TYPE_MAX), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_demod_type(demod_type) \
fe_check_param(((demod_type) >= EXT_DRV_DEMOD_DEV_TYPE_MAX), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define drv_fe_ctrl_check_is_atv(signal_type) \
fe_check_param(((signal_type) != EXT_DRV_FRONTEND_SIG_TYPE_ATV), \
SOC_ERR_FRONTEND_INVALID_PARA, SOC_ERR_FRONTEND_INVALID_PARA)
#define BIT_0 0
#define BIT_1 1
#define BIT_2 2
#define BIT_3 3
#define BIT_4 4
#define BIT_5 5
#define BIT_6 6
#define BIT_7 7
#define BIT_OFFSET_0 0
#define BIT_OFFSET_1 1
#define BIT_OFFSET_2 2
#define BIT_OFFSET_3 3
#define BIT_OFFSET_4 4
#define BIT_OFFSET_5 5
#define BIT_OFFSET_6 6
#define BIT_OFFSET_7 7
#define BIT_OFFSET_8 8
#define BIT_OFFSET_9 9
#define BIT_OFFSET_10 10
#define BIT_OFFSET_11 11
#define BIT_OFFSET_12 12
#define BIT_OFFSET_13 13
#define BIT_OFFSET_14 14
#define BIT_OFFSET_15 15
#define BIT_OFFSET_16 16
#define BIT_OFFSET_17 17
#define BIT_OFFSET_18 18
#define BIT_OFFSET_19 19
#define BIT_OFFSET_20 20
#define BIT_OFFSET_21 21
#define BIT_OFFSET_22 22
#define BIT_OFFSET_23 23
#define BIT_OFFSET_24 24
#define BIT_OFFSET_25 25
#define BIT_OFFSET_26 26
#define BIT_OFFSET_27 27
#define BIT_OFFSET_28 28
#define BIT_OFFSET_29 29
#define BIT_OFFSET_30 30
#define BIT_OFFSET_31 31
#define ARRAY_INDEX_0 0
#define ARRAY_INDEX_1 1
#define ARRAY_INDEX_2 2
#define ARRAY_INDEX_3 3
#define ARRAY_INDEX_4 4
#define ARRAY_INDEX_5 5
#define ARRAY_INDEX_6 6
#define ARRAY_INDEX_7 7
#define ARRAY_INDEX_8 8
#define ARRAY_INDEX_9 9
#define ARRAY_INDEX_10 10
#define ARRAY_INDEX_11 11
#define ARRAY_INDEX_12 12
#define ARRAY_INDEX_13 13
#define ARRAY_INDEX_14 14
#define ARRAY_INDEX_15 15
#define ARRAY_INDEX_16 16
typedef enum {
DRV_FE_TV_SYSTEM_PAL_BG = 0,
DRV_FE_TV_SYSTEM_PAL_DK = 1,
DRV_FE_TV_SYSTEM_PAL_I = 2,
DRV_FE_TV_SYSTEM_PAL_M = 3,
DRV_FE_TV_SYSTEM_PAL_N = 4,
DRV_FE_TV_SYSTEM_SECAM_BG = 5,
DRV_FE_TV_SYSTEM_SECAM_DK = 6,
DRV_FE_TV_SYSTEM_SECAM_L_PRIME = 7,
DRV_FE_TV_SYSTEM_SECAM_LL = 8,
DRV_FE_TV_SYSTEM_NTSC_M = 9,
DRV_FE_TV_SYSTEM_QAM_6MHz = 10,
DRV_FE_TV_SYSTEM_QAM_8MHz = 11,
DRV_FE_TV_SYSTEM_DVBT_1_7MHz = 12,
DRV_FE_TV_SYSTEM_DVBT_6MHz = 13,
DRV_FE_TV_SYSTEM_DVBT_7MHz = 14,
DRV_FE_TV_SYSTEM_DVBT_8MHz = 15,
DRV_FE_TV_SYSTEM_DVBT_10MHz = 16,
DRV_FE_TV_SYSTEM_DTMB_8MHz = 17,
DRV_FE_TV_SYSTEM_ATSC_6MHz = 18,
DRV_FE_TV_SYSTEM_ISDBT_6MHz = 19,
DRV_FE_TV_SYSTEM_FM_RADIO = 20,
DRV_FE_TV_SYSTEM_NTSC_I = 21,
DRV_FE_TV_SYSTEM_NTSC_DK = 22,
DRV_FE_TV_SYSTEM_SAT = 23,
DRV_FE_TV_SYSTEM_DVBT2_8MHz = 24,
DRV_FE_TV_SYSTEM_MAX,
} drv_fe_tv_system;
typedef enum {
I2C_TUNER_TYPE = 0,
I2C_DEMOD_TYPE,
I2C_LNB_TYPE,
I2C_DEVICE_TYPE_MAX
} i2c_device_type;
typedef enum {
ODU_CHANNEL_CHANGE = 0x70,
ODU_CHANNEL_CHANGE_PIN = 0x71,
ODU_UB_AVAIL = 0x7A,
ODU_UB_PIN = 0x7B,
ODU_UB_INUSE = 0x7C,
ODU_UB_FREQ = 0x7D,
ODU_UB_SWITCHES = 0x7E,
ODU_UB_MAX
} unicable2_msg_cmd;
typedef struct {
td_u32 mcu_svn_commit_ver; /* svn code version */
td_char *mcu_git_commit_id; /* git commit id */
td_char *mcu_commit_date; /* svn or git code commit date */
}drv_fe_mcu_info;
typedef struct {
i2c_ext_func *i2c_func;
gpio_i2c_ext_func *gpio_i2c_func;
gpio_ext_func *gpio_func;
} drv_fe_ctrl_func;
typedef struct {
td_s32 (*init)(td_u32 fe_port);
td_s32 (*deinit)(td_u32 fe_port);
td_s32 (*set_system)(td_u32 fe_port, drv_fe_tv_system tv_system);
td_s32 (*set_freq)(td_u32 fe_port, td_u32 freq); /* khz */
td_s32 (*set_freq_symb)(td_u32 fe_port, td_u32 freq, td_u32 symb); /* khz */
td_void (*resume)(td_u32 fe_port);
td_s32 (*monitor)(td_u32 port);
td_s32 (*get_signal_strength)(td_u32 fe_port, td_u32 signal_strength[3]); /* 3:index */
td_s32 (*i2c_read_byte)(td_u32 fe_port, td_u8 reg_addr, td_u8 *reg_val);
td_s32 (*i2c_write_byte)(td_u32 fe_port, td_u8 reg_addr, td_u8 reg_val);
/* for ATV */
td_s32 (*get_pif)(td_u32 *pif);
td_s32 (*set_top_adjust)(td_u32 top);
td_s32 (*set_step)(ext_drv_frontend_atv_step step);
td_s32 (*get_step)(ext_drv_frontend_atv_step *step);
td_s32 (*get_band)(td_u32 frequency, ext_drv_frontend_atv_band *band);
td_s32 (*get_band_freq)(ext_drv_frontend_atv_band band, ext_drv_frontend_atv_band_range *band_freq);
td_s32 (*set_fine_tune)(td_s8 step);
td_bool (*check_tuner_chip_id)(td_void);
} drv_fe_tuner_ops;
typedef struct {
td_s32 (*init)(td_u32 fe_port);
td_s32 (*connect)(td_u32 fe_port, frontend_acc_qam_params *connect_attr);
td_s32 (*deinit)(td_u32 fe_port);
td_s32 (*get_status)(td_u32 fe_port, ext_drv_frontend_lock_status *frontend_status);
td_s32 (*standby)(td_u32 fe_port, td_u32 standby);
td_s32 (*get_signal_info)(td_u32 fe_port, ext_drv_frontend_signal_info *info);
td_s32 (*i2c_bypass)(td_u32 fe_port, td_bool bypass);
td_s32 (*get_ber)(td_u32 fe_port, ext_drv_frontend_scientific_num *num);
td_s32 (*get_per)(td_u32 fe_port, ext_drv_frontend_scientific_num *num);
td_s32 (*get_snr)(td_u32 fe_port, td_s32 *pu32_snr);
td_s32 (*get_signal_strength)(td_u32 fe_port, td_u32 signal_strength[3]); /* 3:index */
td_s32 (*get_signal_quality)(td_u32 fe_port, td_u32 *signal_quality);
td_s32 (*get_freq_symb_offset)(td_u32 fe_port, td_s32 *freq_offset, td_u32 *symb);
td_void (*manage_after_chipreset)(td_u32 fe_port);
td_void (*recalculate_signal_strength)(td_u32 fe_port, td_u32 *strength);
td_void (*connect_timeout)(td_u32 fe_port, td_u32 connect_timeout);
td_s32 (*set_ts_out)(td_u32 fe_port, ext_drv_demod_ts_out *ts_out);
td_s32 (*set_sig_type)(td_u32 fe_port, ext_drv_frontend_sig_type sig_type);
td_bool (*is_ctrl_tuner)(td_u32 fe_port);
td_s32 (*get_rs)(td_u32 u32TunerPort, td_u32 *pu32Rs);
td_s32 (*qamadc_power)(td_u32 fe_port, td_bool power_status);
/* PROC */
td_void (*get_registers)(td_u32 fe_port, td_void *p);
td_s32 (*i2c_read_byte)(td_u32 fe_port, td_u8 u8_reg_addr, td_u8 *reg_val);
td_s32 (*i2c_write_byte)(td_u32 fe_port, td_u8 u8_reg_addr, td_u8 reg_val);
td_s32 (*set_pll_value)(td_u32 pll_value);
td_s32 (*get_cir)(td_u32 fe_port); /* channel_impulse_response */
td_s32 (*catch_data)(td_u32 fe_port, td_u8 u8_catch_sel, td_u8 u8_iq_sel);
td_s32 (*mcu_operate)(td_u32 fe_port, const td_char *p_mcu_cmd);
td_s32 (*mcu_info)(td_u32 fe_port, drv_fe_mcu_info *pst_mcu_info);
/* SAT */
td_s32 (*set_sat_attr)(td_u32 fe_port, ext_drv_frontend_sat_attr *sat_frontend_attr);
td_s32 (*blindscan_init)(td_u32 fe_port, frontend_blindscan_initpara *init_para);
td_s32 (*blindscan_action)(td_u32 fe_port, frontend_blindscan_para *para);
td_s32 (*blindscan_abort)(td_u32 fe_port, td_u32 stop_quit);
td_s32 (*set_lnb_out)(td_u32 fe_port, frontend_lnb_out_level out);
td_s32 (*send_continuous22k)(td_u32 fe_port, td_u32 continuous22k);
td_s32 (*send_tone)(td_u32 fe_port, td_u32 tone);
td_s32 (*diseqc_send_msg)(td_u32 fe_port, ext_drv_frontend_diseqc_send_msg *send_msg);
td_s32 (*diseqc_recv_msg)(td_u32 fe_port, ext_drv_frontend_diseqc_recv_msg *recv_msg);
td_s32 (*set_func_mode)(td_u32 fe_port, frontend_func_mode func_mode);
td_s32 (*tp_verify)(td_u32 fe_port, frontend_tp_verify_params *channel);
td_s32 (*set_isi_id)(td_u32 fe_port, td_u8 isi_id);
td_s32 (*get_isi_id)(td_u32 fe_port, td_u8 stream, td_u8 *isi_id);
td_s32 (*get_stream_num)(td_u32 fe_port, td_u32 *stream_num);
/* DVB-T2 */
td_s32 (*get_plp_num)(td_u32 fe_port, td_u8 *plp_num);
td_s32 (*set_plp_para)(td_u32 fe_port, ext_drv_frontend_dvbt2_plp_para *plp_para);
td_s32 (*get_plp_info)(td_u32 fe_port, td_u32 index, ext_drv_frontend_dvbt2_plp_info *plp_info);
td_s32 (*set_antena_power)(td_u32 port, ext_drv_frontend_ter_antenna_power power);
/* ISDB-T */
td_s32 (*monitor_layers_config)(td_u32 fe_port, ext_drv_frontend_isdbt_receive_config *receive_config);
/* ATV */
td_s32 (*set_pif)(td_u32 pif);
td_s32 (*move_pll_freq)(hal_aifadc_pll_freq en_mode);
} drv_fe_demod_ops;
typedef struct {
td_s32 (*init)(td_u32 fe_port, td_u8 i2c_channel, td_u8 dev_addr);
td_s32 (*deinit)(td_u32 fe_port);
td_s32 (*standby)(td_u32 fe_port, td_u32 standby);
td_s32 (*set_lnb_out)(td_u32 fe_port, frontend_lnb_out_level lnb_out_level);
td_s32 (*i2c_read_byte)(td_u32 fe_port, td_u8 reg_addr, td_u8 *reg_val);
td_s32 (*i2c_write_byte)(td_u32 fe_port, td_u8 reg_addr, td_u8 reg_val);
} drv_fe_lnb_ops;
typedef struct {
ext_drv_frontend_lock_status lock_status;
bool set_ts_out;
ext_drv_demod_ts_out ts_out;
frontend_lnb_out_level lnb_out_level;
td_u32 continuous22k;
} drv_fe_resume_info;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif
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