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1059 lines
30 KiB
1059 lines
30 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2021. All rights reserved.
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* Description: tsr2rcipher hal func impl.
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* Author: Hisilicon
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* Create: 2019-08-02
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*/
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#include "hal_tsr2rcipher.h"
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#include "td_type.h"
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#include "osal_ext.h"
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#include "soc_log.h"
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#include "drv_sys_ext.h"
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#include "drv_tsr2rcipher_define.h"
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#include "drv_tsr2rcipher_func.h"
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#include "drv_tsr2rcipher_reg.h"
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/* Tsr2rcipher Rx Config */
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td_void tsc_hal_rx_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type)
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{
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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/* enable rx interrupt */
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tsc_hal_rx_set_int(mgmt, id, TD_TRUE, TD_FALSE);
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/* rx ctrl */
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tsc_hal_rx_set_ctrl(mgmt, id, buf_type, 0);
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}
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/* Tsr2rcipher Rx DeConfig */
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td_void tsc_hal_rx_de_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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/* disable rx interrupt */
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tsc_hal_rx_set_int(mgmt, id, TD_FALSE, TD_FALSE);
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}
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/* Tsr2rcipher Rx Set Buf */
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td_void tsc_hal_rx_set_buf(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 src_buf_addr, td_u32 src_buf_len)
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{
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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/* rx buffer address */
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tsc_hal_rx_set_buf_addr(mgmt, id, src_buf_addr);
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/* rx buffer len */
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tsc_hal_rx_set_buf_len(mgmt, id, src_buf_len);
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}
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/* Get DspTor status, OSAL_TURE: description queue not full, can configure new description */
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td_bool tsc_hal_rx_get_dsp_tor_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_RX_DSPTOR_CTRL reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return TD_FALSE;
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}
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tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, TD_FALSE);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_ctrl(id));
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return (reg.bits.rx_dsptor_full == 0x0);
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}
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/* Set the buffer start address, OSAL_TURE: description queue not full, can configure new description */
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td_void tsc_hal_rx_set_buf_addr(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 src_addr)
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{
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U_RX_DSPTOR_START_ADDR reg_addr;
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U_TSC_RX_CTRL reg_ctrl;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg_addr.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_start_addr(id));
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reg_ctrl.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id));
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/* risk here */
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reg_addr.bits.rx_dsptor_start_addr = src_addr & 0x00000000FFFFFFFF; /* 4K align, and 16 bytes align next version */
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reg_ctrl.bits.rx_session_id = (src_addr & 0x0000000F00000000) >> 32; /* right shift 32 bits to get high 4 bits */
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tsc_write_reg_rx(mgmt->io_base, rx_dsptor_start_addr(id), reg_addr.u32);
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tsc_write_reg_rx(mgmt->io_base, tsc_rx_ctrl(id), reg_ctrl.u32);
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}
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/* Set the buffer Len */
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td_void tsc_hal_rx_set_buf_len(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u32 src_len)
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{
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U_RX_DSPTOR_LENGTH reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id));
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reg.bits.rx_dsptor_length = src_len / TSR2RCIPHER_TS_PACKAGE_LEN; /* ts package number */
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reg.bits.rx_dsptor_cfg = 1;
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tsc_write_reg_rx(mgmt->io_base, rx_dsptor_length(id), reg.u32);
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}
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/* Add the Rx Dsc */
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td_void tsc_hal_rx_add_dsc(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_RX_DSPTOR_LENGTH reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id));
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reg.bits.rx_dsptor_cfg = 1;
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tsc_write_reg_rx(mgmt->io_base, rx_dsptor_length(id), reg.u32);
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tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id)));
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}
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/* Set Rx Ctrl */
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td_void tsc_hal_rx_set_ctrl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type,
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td_u32 rx_pkg_th)
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{
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U_TSC_RX_CTRL reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id));
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reg.bits.rx_buf_type = buf_type;
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reg.bits.rx_pkt_int_level = rx_pkg_th;
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tsc_write_reg_rx(mgmt->io_base, tsc_rx_ctrl(id), reg.u32);
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tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id)));
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}
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/* Set Rx Ctrl */
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td_void tsc_hal_rx_set_int(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool dsc_rd, td_bool rx_pkt)
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{
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U_IENA_RX reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, iena_rx(id));
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reg.bits.iena_rx_dsptor_done = (TD_TRUE == dsc_rd ? 1 : 0);
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reg.bits.iena_rx_pkt_cnt = (TD_TRUE == rx_pkt ? 1 : 0);
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tsc_write_reg_rx(mgmt->io_base, iena_rx(id), reg.u32);
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tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, iena_rx(id)));
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}
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/* Get Rx Dsc Rd Total Int status */
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td_u32 tsc_hal_rx_get_dsc_rd_total_int_status(const struct tsr2rcipher_mgmt *mgmt)
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{
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U_RX_INT_TYPE reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return 0;
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}
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, RX_INT_TYPE);
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return reg.bits.rx_dsptor_done_int;
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}
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/* Get Rx Pkt cnt Total Int status */
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td_u32 tsc_hal_rx_get_pkt_cnt_total_int_status(const struct tsr2rcipher_mgmt *mgmt)
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{
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U_RX_INT_TYPE reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return 0;
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}
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, RX_INT_TYPE);
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return reg.bits.rx_pkt_cnt_int;
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}
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/* Get the Dsc Rd interrupt status */
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td_u32 tsc_hal_rx_get_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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td_u32 reg_index;
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td_u32 bit_offset;
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td_u32 reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return 0;
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}
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tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0);
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reg_index = id / INT_FLAG_REG_NUM;
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bit_offset = id % INT_FLAG_REG_NUM;
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reg = tsc_read_reg_rx(mgmt->io_base, ista_rx_dsptor0(reg_index));
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return (reg & (1U << bit_offset));
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}
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/* Cls Rx Dsc Rd Int status */
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td_void tsc_hal_rx_cls_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_IRAW_RX reg;
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U_IRAW_RX reg_cls;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = 0;
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reg_cls.u32 = 0;
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reg.bits.iraw_rx_dsptor_done = 1;
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tsc_write_reg_rx(mgmt->io_base, iraw_rx(id), reg.u32);
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}
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/* Get the Rx Pkt cnt interrupt status */
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td_u32 tsc_hal_rx_get_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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td_u32 reg_index;
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td_u32 bit_offset;
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td_u32 reg;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return 0;
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}
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tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0);
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reg_index = id / INT_FLAG_REG_NUM;
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bit_offset = id % INT_FLAG_REG_NUM;
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reg = tsc_read_reg_rx(mgmt->io_base, ista_rx_pkt_cnt0(reg_index));
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return (reg & (1U << bit_offset));
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}
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/* Cls Rx Pkt cnt Int status */
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td_void tsc_hal_rx_cls_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_IRAW_RX reg;
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U_IRAW_RX reg_cls;
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if (mgmt == TD_NULL) {
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soc_log_err("mgmt is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = 0;
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reg_cls.u32 = 0;
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reg.bits.iraw_rx_pkt_cnt = 1;
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tsc_write_reg_rx(mgmt->io_base, iraw_rx(id), reg.u32);
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}
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/* Get the Rx Total Dsc Rd interrupt Register value */
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td_void tsc_hal_rx_get_dsc_rd_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array)
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{
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td_u32 i;
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td_u32 array_cnt;
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if ((mgmt == TD_NULL) || (value_array == TD_NULL)) {
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soc_log_err("para is null!\n");
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return;
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}
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if ((td_s32)mgmt->ch_cnt <= 1) {
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return;
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}
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array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM;
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for (i = 0; i < array_cnt; i++) {
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value_array[i] = tsc_read_reg_rx(mgmt->io_base, ista_rx_dsptor0(i));
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}
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}
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/* Get the Total Pkt cnt interrupt regitster value */
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td_void tsc_hal_rx_get_pkt_cnt_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array)
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{
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td_u32 i;
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td_u32 array_cnt;
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if ((mgmt == TD_NULL) || (value_array == TD_NULL)) {
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soc_log_err("para is null!\n");
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return;
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}
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if ((td_s32)mgmt->ch_cnt <= 1) {
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return;
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}
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array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM;
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for (i = 0; i < array_cnt; i++) {
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value_array[i] = tsc_read_reg_rx(mgmt->io_base, ista_rx_pkt_cnt0(i));
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}
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}
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/* Set Rx Mode Ctrl */
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td_void tsc_hal_set_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, struct tsr2rcipher_r_ch *rch,
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enum tsc_crypt_type crypt_type)
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{
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U_TSC_MODE_CTRL reg;
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if ((mgmt == TD_NULL) || (rch == TD_NULL)) {
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soc_log_err("para is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(rch->base.id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id));
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reg.bits.key_id = (rch->ks_handle & 0x000000ff);
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reg.bits.dsc_type = crypt_type;
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reg.bits.core_sel = rch->core_type;
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reg.bits.pl_raw_sel = rch->mode;
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if (rch->is_odd_key == TD_TRUE) {
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reg.bits.odd_even_sel = 1;
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} else {
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reg.bits.odd_even_sel = 0;
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}
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if (rch->is_crc_check == TD_TRUE) {
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reg.bits.tsc_crc_en = 1;
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} else {
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reg.bits.tsc_crc_en = 0;
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}
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tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id), reg.u32);
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reg.bits.tsc_rx_sec_attr = 1;
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reg.bits.tsc_tx_sec_attr = 1;
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tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id)));
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}
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/* Set Rx Mode Ctrl */
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td_void tsc_hal_en_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_TSC_MODE_CTRL reg;
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if (mgmt == TD_NULL) {
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soc_log_err("para is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id));
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reg.bits.tsc_chn_en = 1;
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tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(id), reg.u32);
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tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id)));
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}
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/* Set Rx Mode Ctrl */
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td_void tsc_hal_dis_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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U_TSC_MODE_CTRL reg;
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if (mgmt == TD_NULL) {
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soc_log_err("para is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id));
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reg.bits.tsc_chn_en = 0;
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tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(id), reg.u32);
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}
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td_void tsc_hal_clr_chan(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
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{
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td_u32 i = 0;
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u_tsc_clear_req reg;
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if (mgmt == TD_NULL) {
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soc_log_err("para is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ);
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reg.bits.tsc_clear_chn_id = id;
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reg.bits.tsc_clear_chn_req = 1;
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tsc_write_reg_rx(mgmt->io_base, TSC_CLEAR_REQ, reg.u32);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ);
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while (reg.bits.tsc_clear_chn_req != 0 && (i++ <= TSC_CHAN_CLEAR_TIMEOUT_CNT)) {
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osal_msleep(1);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ);
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}
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if (i >= TSC_CHAN_CLEAR_TIMEOUT_CNT) {
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soc_log_err("clear chan time out!\n");
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}
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}
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td_void tsc_hal_lock_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool is_tee_lock)
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{
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u_rx_sec_attr reg;
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if (mgmt == TD_NULL) {
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soc_log_err("para is null!\n");
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return;
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}
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tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
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reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_sec_attr(id));
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if (is_tee_lock == TD_TRUE) {
|
|
reg.bits.tsc_chn_tee_lock = 1;
|
|
} else {
|
|
reg.bits.tsc_chn_ree_lock = 1;
|
|
}
|
|
|
|
tsc_write_reg_rx(mgmt->io_base, rx_sec_attr(id), reg.u32);
|
|
}
|
|
|
|
td_void tsc_hal_lock_deconfig(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
u_rx_sec_attr reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_sec_attr(id));
|
|
reg.bits.tsc_chn_tee_lock = 0;
|
|
reg.bits.tsc_chn_ree_lock = 0;
|
|
|
|
tsc_write_reg_rx(mgmt->io_base, rx_sec_attr(id), reg.u32);
|
|
}
|
|
|
|
/* Tsr2rcipher Tx Config */
|
|
td_void tsc_hal_tx_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type)
|
|
{
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
/* enable tx interrupt */
|
|
tsc_hal_tx_set_int(mgmt, id, TD_TRUE, TD_FALSE);
|
|
|
|
/* tx ctrl */
|
|
tsc_hal_tx_set_ctrl(mgmt, id, buf_type, 0);
|
|
}
|
|
|
|
/* Tsr2rcipher Tx DeConfig */
|
|
td_void tsc_hal_tx_de_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
/* disable rx interrupt */
|
|
tsc_hal_tx_set_int(mgmt, id, TD_FALSE, TD_FALSE);
|
|
}
|
|
|
|
/* Tsr2rcipher Tx Set Buffer */
|
|
td_void tsc_hal_tx_set_buf(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 dst_buf_addr, td_u32 dst_buf_len)
|
|
{
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
/* tx buffer address */
|
|
tsc_hal_tx_set_buf_addr(mgmt, id, dst_buf_addr);
|
|
|
|
/* tx buffer len */
|
|
tsc_hal_tx_set_buf_len(mgmt, id, dst_buf_len);
|
|
}
|
|
|
|
/* Get DspTor status, OSAL_TURE: description queue not full, can configure new description */
|
|
td_bool tsc_hal_tx_get_dsp_tor_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
U_TX_DSPTOR_CTRL reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return TD_FALSE;
|
|
}
|
|
tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, TD_FALSE);
|
|
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_ctrl(id));
|
|
return (reg.bits.tx_dsptor_full == 0x0);
|
|
}
|
|
|
|
/* Set the buffer start address */
|
|
td_void tsc_hal_tx_set_buf_addr(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 dst_addr)
|
|
{
|
|
U_TX_DSPTOR_START_ADDR reg_addr;
|
|
U_TSC_TX_CTRL reg_ctrl;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg_addr.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_start_addr(id));
|
|
reg_ctrl.u32 = tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id));
|
|
|
|
/* risk here */
|
|
reg_addr.bits.tx_dsptor_start_addr = dst_addr & 0x00000000FFFFFFFF; /* 4K align, and 16 bytes align next version */
|
|
reg_ctrl.bits.tx_session_id = (dst_addr & 0x0000000F00000000) >> 32; /* right shift 32 bits to get high 4 bits */
|
|
|
|
tsc_write_reg_tx(mgmt->io_base, tx_dsptor_start_addr(id), reg_addr.u32);
|
|
tsc_write_reg_tx(mgmt->io_base, TSC_TX_CTRL(id), reg_ctrl.u32);
|
|
}
|
|
|
|
/* Set the buffer Len */
|
|
td_void tsc_hal_tx_set_buf_len(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u32 dst_len)
|
|
{
|
|
U_TX_DSPTOR_LENGTH reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id));
|
|
reg.bits.tx_dsptor_length = dst_len / TSR2RCIPHER_TS_PACKAGE_LEN; /* ts package number */
|
|
reg.bits.tx_dsptor_cfg = 1;
|
|
|
|
tsc_write_reg_tx(mgmt->io_base, tx_dsptor_length(id), reg.u32);
|
|
}
|
|
|
|
/* Add the Rx Dsc */
|
|
td_void tsc_hal_tx_add_dsc(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
U_TX_DSPTOR_LENGTH reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id));
|
|
reg.bits.tx_dsptor_cfg = 1;
|
|
|
|
tsc_write_reg_rx(mgmt->io_base, tx_dsptor_length(id), reg.u32);
|
|
|
|
tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id)));
|
|
}
|
|
|
|
/* Set Tx Ctrl */
|
|
td_void tsc_hal_tx_set_ctrl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type,
|
|
td_u32 tx_pkg_th)
|
|
{
|
|
U_TSC_TX_CTRL reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id));
|
|
reg.bits.tx_buf_type = buf_type;
|
|
reg.bits.tx_pkt_int_level = tx_pkg_th;
|
|
reg.bits.tx_press_dis = 0x1; /* disable press */
|
|
|
|
tsc_write_reg_tx(mgmt->io_base, TSC_TX_CTRL(id), reg.u32);
|
|
|
|
tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id)));
|
|
}
|
|
|
|
/* Set Tx interrupt */
|
|
td_void tsc_hal_tx_set_int(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool dsc_rd, td_bool tx_pkt)
|
|
{
|
|
U_IENA_TX reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, IENA_TX(id));
|
|
reg.bits.iena_tx_dsptor_done = (dsc_rd == TD_TRUE ? 1 : 0);
|
|
reg.bits.iena_tx_pkt_cnt = (tx_pkt == TD_TRUE ? 1 : 0);
|
|
|
|
tsc_write_reg_tx(mgmt->io_base, IENA_TX(id), reg.u32);
|
|
|
|
tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, IENA_TX(id)));
|
|
}
|
|
|
|
/* Get Tx Dsc Rd Total Int status */
|
|
td_u32 tsc_hal_tx_get_dsc_rd_total_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TX_INT_TYPE reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, TX_INT_TYPE);
|
|
return reg.bits.tx_dsptor_done_int;
|
|
}
|
|
|
|
/* Get Tx Pkt cnt Total Int status */
|
|
td_u32 tsc_hal_tx_get_pkt_cnt_total_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TX_INT_TYPE reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = tsc_read_reg_tx(mgmt->io_base, TX_INT_TYPE);
|
|
return reg.bits.tx_pkt_cnt_int;
|
|
}
|
|
|
|
/* Get the Tx Dsc Rd interrupt status */
|
|
td_u32 tsc_hal_tx_get_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
td_u32 reg_index;
|
|
td_u32 bit_offset;
|
|
td_u32 reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0);
|
|
|
|
reg_index = id / INT_FLAG_REG_NUM;
|
|
bit_offset = id % INT_FLAG_REG_NUM;
|
|
|
|
reg = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_DSPTOR0(reg_index));
|
|
|
|
return (reg & (1U << bit_offset));
|
|
}
|
|
|
|
/* Cls Tx Dsc Rd Int status */
|
|
td_void tsc_hal_tx_cls_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
U_IRAW_TX reg;
|
|
U_IRAW_TX reg_cls;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = 0;
|
|
reg_cls.u32 = 0;
|
|
reg.bits.iraw_tx_dsptor_done = 1;
|
|
|
|
tsc_write_reg_tx(mgmt->io_base, IRAW_TX(id), reg.u32);
|
|
}
|
|
|
|
/* Get the Tx Pkt cnt interrupt status */
|
|
td_u32 tsc_hal_tx_get_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
td_u32 reg_index;
|
|
td_u32 bit_offset;
|
|
td_u32 reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0);
|
|
|
|
reg_index = id / INT_FLAG_REG_NUM;
|
|
bit_offset = id % INT_FLAG_REG_NUM;
|
|
|
|
reg = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_PKT_CNT0(reg_index));
|
|
|
|
return (reg & (1U << bit_offset));
|
|
}
|
|
|
|
/* Cls Tx Pkt Cnt Int status */
|
|
td_void tsc_hal_tx_cls_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id)
|
|
{
|
|
U_IRAW_TX reg;
|
|
U_IRAW_TX reg_cls;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = 0;
|
|
reg_cls.u32 = 0;
|
|
reg.bits.iraw_tx_pkt_cnt = 1;
|
|
|
|
tsc_write_reg_rx(mgmt->io_base, IRAW_TX(id), reg.u32);
|
|
|
|
tsc_com_equal(reg_cls.u32, tsc_read_reg_tx(mgmt->io_base, IRAW_TX(id)));
|
|
}
|
|
|
|
/* Get the Total Dsc Rd interrupt Register value */
|
|
td_void tsc_hal_tx_get_dsc_rd_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array)
|
|
{
|
|
td_u32 i;
|
|
td_u32 array_cnt;
|
|
|
|
if ((mgmt == TD_NULL) || (value_array == TD_NULL)) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
if ((td_s32)mgmt->ch_cnt <= 1) {
|
|
return;
|
|
}
|
|
array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM;
|
|
|
|
for (i = 0; i < array_cnt; i++) {
|
|
value_array[i] = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_DSPTOR0(i));
|
|
}
|
|
}
|
|
|
|
/* Get the Total Pkt interrupt regitster value */
|
|
td_void tsc_hal_tx_get_pkt_cnt_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array)
|
|
{
|
|
td_u32 i;
|
|
td_u32 array_cnt;
|
|
|
|
if ((mgmt == TD_NULL) || (value_array == TD_NULL)) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
if ((td_s32)mgmt->ch_cnt <= 1) {
|
|
return;
|
|
}
|
|
array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM;
|
|
|
|
for (i = 0; i < array_cnt; i++) {
|
|
value_array[i] = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_PKT_CNT0(i));
|
|
}
|
|
}
|
|
|
|
/* Set Top interrupt */
|
|
td_void tsc_hal_top_set_int(const struct tsr2rcipher_mgmt *mgmt, td_bool rx_int, td_bool tx_int, td_bool cipher_int)
|
|
{
|
|
U_TSC_IENA reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IENA);
|
|
reg.bits.rx2cpu_iena = (rx_int == TD_TRUE ? 1 : 0);
|
|
reg.bits.tx2cpu_iena = (tx_int == TD_TRUE ? 1 : 0);
|
|
reg.bits.cipher2cpu_iena = (cipher_int == TD_TRUE ? 1 : 0);
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IENA, reg.u32);
|
|
|
|
tsc_com_equal(reg.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_IENA));
|
|
}
|
|
|
|
/* Get Top Rx interrupt status */
|
|
td_u32 tsc_hal_top_get_rx_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_ISTA reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA);
|
|
|
|
return reg.bits.rx2cpu_ista;
|
|
}
|
|
|
|
/* Get Top Rx Raw interrupt status */
|
|
td_u32 tsc_hal_top_get_rx_raw_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_IRAW reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW);
|
|
|
|
return reg.bits.rx2cpu_iraw;
|
|
}
|
|
|
|
/* Cls Top Rx interrupt status */
|
|
td_void tsc_hal_top_cls_rx_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_IRAW reg;
|
|
U_TSC_IRAW reg_cls;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
reg.u32 = 0;
|
|
reg_cls.u32 = 0;
|
|
reg.bits.rx2cpu_iraw = 1;
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32);
|
|
}
|
|
|
|
/* Get Top Tx interrupt status */
|
|
td_u32 tsc_hal_top_get_tx_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_ISTA reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA);
|
|
|
|
return reg.bits.tx2cpu_ista;
|
|
}
|
|
|
|
/* Get Top Tx Raw interrupt status */
|
|
td_u32 tsc_hal_top_get_tx_raw_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_IRAW reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW);
|
|
|
|
return reg.bits.tx2cpu_iraw;
|
|
}
|
|
|
|
/* Cls Top Tx interrupt status */
|
|
td_void tsc_hal_top_cls_tx_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_IRAW reg;
|
|
U_TSC_IRAW reg_cls;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
reg.u32 = 0;
|
|
reg_cls.u32 = 0;
|
|
reg.bits.tx2cpu_iraw = 1;
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32);
|
|
}
|
|
|
|
/* Get Top Cipher interrupt status */
|
|
td_u32 tsc_hal_top_get_cipher_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_ISTA reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return 0;
|
|
}
|
|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA);
|
|
|
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return reg.bits.cipher2cpu_ista;
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}
|
|
|
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/* Get Top Cipher interrupt status */
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td_u32 tsc_hal_top_get_cipher_raw_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
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|
U_TSC_IRAW reg;
|
|
|
|
if (mgmt == TD_NULL) {
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|
soc_log_err("para is null!\n");
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|
return 0;
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|
}
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|
reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW);
|
|
|
|
return reg.bits.cipher2cpu_iraw;
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}
|
|
|
|
/* Cls Top Rx interrupt status */
|
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td_void tsc_hal_top_cls_cipher_int_status(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_IRAW reg;
|
|
U_TSC_IRAW reg_cls;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
reg.u32 = 0;
|
|
reg_cls.u32 = 0;
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|
reg.bits.cipher2cpu_iraw = 1;
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32);
|
|
}
|
|
|
|
td_void tsc_hal_init_hw(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
#ifndef CONFIG_SOCT_TEE_SUPPORT
|
|
tsc_tee_crg_ctrl tee_crg_ctrl;
|
|
|
|
if ((mgmt == TD_NULL) || (mgmt->tee_crg_ctrl_base == TD_NULL)) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tee_crg_ctrl.u32 = tsc_read_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET);
|
|
|
|
tee_crg_ctrl.bits.tsc_srst_req = 1;
|
|
tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32);
|
|
|
|
tee_crg_ctrl.bits.tsc_cken = 1;
|
|
tee_crg_ctrl.bits.tsc_srst_req = 0;
|
|
tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32);
|
|
#endif
|
|
|
|
return;
|
|
}
|
|
|
|
td_void tsc_hal_de_init_hw(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
#ifndef CONFIG_SOCT_TEE_SUPPORT
|
|
tsc_tee_crg_ctrl tee_crg_ctrl;
|
|
|
|
if ((mgmt == TD_NULL) || (mgmt->tee_crg_ctrl_base == TD_NULL)) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tee_crg_ctrl.u32 = tsc_read_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET);
|
|
|
|
tee_crg_ctrl.bits.tsc_srst_req = 1;
|
|
tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32);
|
|
|
|
tee_crg_ctrl.bits.tsc_cken = 0;
|
|
tee_crg_ctrl.bits.tsc_srst_req = 0;
|
|
tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32);
|
|
#endif
|
|
|
|
return;
|
|
}
|
|
|
|
td_void tsc_hal_en_mmu(struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_MMU_NOSEC_EN mmu_nosec_en;
|
|
td_ulong cb_ttbr = 0;
|
|
td_ulong err_rd_addr = 0;
|
|
td_ulong err_wr_addr = 0;
|
|
td_u32 i;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
if (ext_drv_sys_get_capability(EXT_SYS_CAP_TYPE_SMMU_SUPPORT) != TD_TRUE) {
|
|
return;
|
|
}
|
|
|
|
osal_mem_get_nssmmu_pgtinfo(&cb_ttbr, &err_rd_addr, &err_wr_addr);
|
|
mgmt->cb_ttbr = cb_ttbr;
|
|
|
|
/* hw restrict cb_ttbr must be 16bytes align. */
|
|
WARN_ON(cb_ttbr % 16);
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_TLB, cb_ttbr >> 4); /* right shift 4 bits to get base table */
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_NOSEC_EADDR_L, (td_u32)(err_rd_addr & 0xFFFFFFFFU));
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_NOSEC_EADDR_L, (td_u32)(err_wr_addr & 0xFFFFFFFFU));
|
|
/* right shift 32 bits to get high 4 bits */
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_NOSEC_EADDR_H, (td_u32)((err_rd_addr >> 32) & 0xFU));
|
|
/* right shift 32 bits to get high 4 bits */
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_NOSEC_EADDR_H, (td_u32)((err_wr_addr >> 32) & 0xFU));
|
|
|
|
mmu_nosec_en.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN);
|
|
mmu_nosec_en.bits.sw_nosec_mmu_en = 1;
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN, mmu_nosec_en.u32);
|
|
|
|
tsc_com_equal(mmu_nosec_en.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN));
|
|
|
|
for (i = 0; i < 8; i++) { /* the num of clear rx page table register is 8 */
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_CLR(i), 0xFFFFFFFF);
|
|
}
|
|
|
|
for (i = 0; i < 8; i++) { /* the num of clear tx page table register is 8 */
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_CLR(i), 0xFFFFFFFF);
|
|
}
|
|
}
|
|
|
|
td_void tsc_hal_dis_mmu(const struct tsr2rcipher_mgmt *mgmt)
|
|
{
|
|
U_TSC_MMU_NOSEC_EN mmu_nosec_en;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
if (ext_drv_sys_get_capability(EXT_SYS_CAP_TYPE_SMMU_SUPPORT) != TD_TRUE) {
|
|
return;
|
|
}
|
|
|
|
mmu_nosec_en.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN);
|
|
mmu_nosec_en.bits.sw_nosec_mmu_en = 0;
|
|
|
|
TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN, mmu_nosec_en.u32);
|
|
|
|
tsc_com_equal(mmu_nosec_en.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN));
|
|
}
|
|
|
|
/* Set the Mdsc Enable register */
|
|
td_void tsc_hal_mdscset_en(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool ca_en, td_bool ca_chan_scr_en)
|
|
{
|
|
U_MDSC_EN reg;
|
|
|
|
if (mgmt == TD_NULL) {
|
|
soc_log_err("para is null!\n");
|
|
return;
|
|
}
|
|
tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt);
|
|
|
|
reg.u32 = TSC_READ_REG_MDSC(mgmt->io_base, MDSC_EN);
|
|
|
|
reg.bits.ca_en = ca_en ? 1 : 0;
|
|
reg.bits.ts_ctrl_dsc_change_en = ca_chan_scr_en ? 1 : 0;
|
|
|
|
TSC_WRITE_REG_MDSC(mgmt->io_base, MDSC_EN, reg.u32);
|
|
|
|
tsc_com_equal(reg.u32, TSC_READ_REG_MDSC(mgmt->io_base, MDSC_EN));
|
|
}
|
|
|