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263 lines
8.5 KiB
263 lines
8.5 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2020. All rights reserved.
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* Description: mailbox driver for liteos
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*/
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#ifndef _DRV_MAILBOX_H_
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#define _DRV_MAILBOX_H_
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#include "los_mbx.h"
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#ifdef CONFIG_DRIVERS_MBX_DMCU
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#include <los_hwi.h>
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#include <los_mux.h>
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#include "delay.h"
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#else
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#include "los_list.h"
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#include "los_mux.h"
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#include "los_delay.h"
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#endif
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#ifdef __cplusplus
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#if __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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#define SUPPORT_MBX_INTERRUPT
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#define MAILBOX_VERSION_OFFSET 0x0
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/* acpu to vmcu0 */
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#ifdef CHIP_TYPE_RESERVED23
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#define MBX_VMCU0_BASE_ADDR 0x00dfb000
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#else
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#define MBX_VMCU0_BASE_ADDR 0x0129b000
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#endif
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#define MBX_VMCU1_BASE_ADDR 0x012bb000
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#define ACPU_TO_VMCU_HEAD_OFFSET (0x0020 / 4)
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#define ACPU_TO_VMCU_ARGS_OFFSET (0x0040 / 4)
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#define ACPU_TO_VMCU_ARGS_NUM (16 * 4)
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#define ACPU_TO_VMCU_SEND_OFFSET (0x0400 / 4)
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#define ACPU_INTR_FROM_VMCU_OFFSET (0x0418 / 4)
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/* vmcu0 to acpu */
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#define VMCU_TO_ACPU_HEAD_OFFSET (0x0100 / 4)
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#define VMCU_TO_ACPU_ARGS_OFFSET (0x0420 / 4)
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#define VMCU_TO_ACPU_ARGS_V2_OFFSET (0x0110 / 4)
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#define VMCU_TO_ACPU_ARGS_NUM (12 * 4)
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#define VMCU_TO_ACPU_ARGS_V2_NUM (16 * 4)
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#define VMCU_TO_ACPU_SEND_OFFSET (0x0410 / 4)
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#define VMCU_INTR_FROM_ACPU_OFFSET (0x0408 / 4)
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/* tcpu to vmcu0 */
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#define TCPU_TO_VMCU_HEAD_OFFSET (0x0200 / 4)
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#define TCPU_TO_VMCU_ARGS_OFFSET (0x0240 / 4)
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#define TCPU_TO_VMCU_ARGS_NUM (16 * 4)
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#define TCPU_TO_VMCU_SEND_OFFSET (0x0404 / 4)
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#define TCPU_INTR_FROM_VMCU_OFFSET (0x041C / 4)
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/* vmcu0 to tcpu */
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#define VMCU_TO_TCPU_HEAD_OFFSET (0x0300 / 4)
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#define VMCU_TO_TCPU_ARGS_OFFSET (0x0310 / 4)
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#define VMCU_TO_TCPU_ARGS_NUM (4 * 4)
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#define VMCU_TO_TCPU_SEND_OFFSET (0x0414 / 4)
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#define VMCU_INTR_FROM_TCPU_OFFSET (0x040C / 4)
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#define MBX_IRQ_ACPU2VMCU (26 + 13)
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#define ACPU2VMCU_IRQ_NAME "ACPU2VMCU_IRQ"
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#define MBX_IRQ_TCPU2VMCU (26 + 12)
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#define TCPU2VMCU_IRQ_NAME "TCPU2VMCU_IRQ"
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/* acpu to dmcu0 */
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#ifndef CONFIG_MBX_BASE_ADDR_DMCU
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#define CONFIG_MBX_BASE_ADDR_DMCU 0x117B000
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#endif
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#define MBX_ACPU_DMCU0_BASE_ADDR CONFIG_MBX_BASE_ADDR_DMCU
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#define ACPU_TO_DMCU_HEAD_OFFSET (0x0020 / 4)
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#define ACPU_TO_DMCU_ARGS_OFFSET (0x0040 / 4)
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#define ACPU_TO_DMCU_ARGS_NUM (16 * 4)
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#define ACPU_TO_DMCU_SEND_OFFSET (0x0400 / 4)
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#define ACPU_INTR_FROM_DMCU_OFFSET (0x0418 / 4)
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/* dmcu0 to acpu */
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#define DMCU_TO_ACPU_HEAD_OFFSET (0x0100 / 4)
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#define DMCU_TO_ACPU_ARGS_V2_OFFSET (0x0110 / 4)
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#define DMCU_TO_ACPU_ARGS_OFFSET (0x0420 / 4)
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#define DMCU_TO_ACPU_ARGS_V2_NUM (16 * 4)
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#define DMCU_TO_ACPU_ARGS_NUM (12 * 4)
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#define DMCU_TO_ACPU_SEND_OFFSET (0x0410 / 4)
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#define DMCU_INTR_FROM_ACPU_OFFSET (0x0408 / 4)
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#define MBX_IRQ_ACPU2DMCU (26 + 12)
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#define DMCU2ACPU_IRQ_NAME "ACPU2DMCU_IRQ"
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#define SOC_ERRCODE_DEF(moduleid, errid) (td_u32)(0x80000000 | ((moduleid) << 16) | (errid))
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#define SOC_MAILBOX_ID 0x6D
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#define SOC_MBX_SUCCESS 0
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#define SOC_MBX_FAILURE (-1)
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#define MBX_DELAY_TIME 10
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#define MBX_RX_BUFF_SIZE 4100
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#define MBX_TX_BUFF_SIZE 0
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#define SOC_ERR_MAILBOX_NOT_INIT SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0001)
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#define SOC_ERR_MAILBOX_INVALID_HANDLE SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0002)
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#define SOC_ERR_MAILBOX_INVALID_PTR SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0003)
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#define SOC_ERR_MAILBOX_INVALID_PARA SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0004)
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#define SOC_ERR_MAILBOX_INVALID_FLAG SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0005)
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#define SOC_ERR_MAILBOX_INVALID_RECEIVER SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0006)
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#define SOC_ERR_MAILBOX_NO_MEMORY SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0007)
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#define SOC_ERR_MAILBOX_NOT_SUPPORT SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0008)
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#define SOC_ERR_MAILBOX_ERR_RECEIVE SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0009)
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#define SOC_ERR_MAILBOX_UNEXPECTED_RECEIVE_LEN SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000A)
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#define SOC_ERR_MAILBOX_CRC_CHECK_ERROR SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000B)
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#define SOC_ERR_MAILBOX_UNKNOWN_CMD SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000C)
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#define SOC_ERR_MAILBOX_NO_SESSION SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000D)
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#define SOC_ERR_MAILBOX_TIMEOUT SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000E)
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#define SOC_ERR_MAILBOX_UNKNOWN SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x000F)
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#define SOC_ERR_MAILBOX_PENDING SOC_ERRCODE_DEF(SOC_MAILBOX_ID, 0x0010)
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#define SESSION_BUSY (1 << 0)
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#define SESSION_ID_SIDE0(session_id) (((session_id) >> 4) & 0xF)
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#define SESSION_ID_SIDE1(session_id) ((session_id) & 0xF)
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#define SESSION_ID_NUM(session_id) (((session_id) >> 8) & 0xFF)
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#define SESSION_ID_PORT(session_id) (((session_id) >> 16) & 0x7F)
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#define SESSION_ID_HANDLE(session_id) (((session_id) >> 8) & 0x7FFF)
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#define GEN_SESSION_HANDLE(num, port) (((num) & 0xFF) | ((port) & 0x7F) << 8)
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#define SESSION_HANDLE_NUM(handle) ((handle) & 0xFF)
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#define SESSION_HANDLE_PORT(handle) (((handle) >> 8) & 0x7F)
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struct buffer {
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td_u8 *addr;
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td_u32 size;
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td_u32 rd_idx;
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td_u32 wr_idx;
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};
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struct reg {
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td_u32 *version;
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td_u32 *head;
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td_u32 *argv;
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td_u32 argv_size;
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td_u32 *trigger_rx;
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td_u32 *pending;
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td_u32 *lock;
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};
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struct session {
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td_u32 num;
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td_u32 port;
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td_u32 rx_status;
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td_s32 tx_status;
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struct buffer rx_buf;
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struct buffer tx_buf;
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struct reg *rx_reg;
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struct reg *tx_reg;
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session_callback func;
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const td_void *data;
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LOS_DL_LIST node;
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};
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union msg_head {
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struct {
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td_u32 reserved : 9; /* [8:0] */
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td_u32 port : 7; /* [15:9] */
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td_u32 num : 8; /* [23:16] */
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td_u32 msg_len : 7; /* [30:24] */
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td_u32 ongoing : 1; /* [31] */
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} bits;
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td_u32 head;
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};
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struct addr_info {
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td_u32 *base_addr;
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td_u32 *rx_head_addr;
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};
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struct mailbox {
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enum cpu_id local_cpu;
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td_u32 initalized;
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td_u32 list_lock;
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LOS_DL_LIST list_head;
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struct addr_info acpu_vmcu0;
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struct addr_info tcpu_vmcu0;
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td_u32 tx_acpu_lock;
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td_u32 tx_tcpu_lock;
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struct addr_info acpu_dmcu0;
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td_u32 tx_dmcu0_lock;
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td_u32 dmcu0_irq;
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};
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static inline void mutex_lock(td_u32 *lock)
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{
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LOS_MuxPend(*lock, LOS_WAIT_FOREVER);
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return;
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}
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static inline void mutex_unlock(td_u32 *lock)
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{
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LOS_MuxPost(*lock);
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return;
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}
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static inline void spin_lock_irqsave(td_u32 *lock, td_ulong *flag)
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{
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*flag = LOS_IntLock();
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LOS_TaskLock();
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return;
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}
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static inline void spin_unlock_irqrestore(td_u32 *lock, td_ulong *flag)
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{
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LOS_TaskUnlock();
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LOS_IntRestore(*flag);
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return;
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}
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static inline td_u32 readl(const td_u32 *addr)
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{
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if (addr == NULL) {
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return SOC_ERR_MAILBOX_INVALID_PTR;
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}
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__asm__ __volatile__("fence");
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return GET_UINT32(addr);
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}
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static inline void writel(td_u32 value, const td_u32 *addr)
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{
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if (addr == NULL) {
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return;
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}
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WRITE_UINT32(value, addr);
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__asm__ __volatile__("fence");
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}
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#define MBX_ERR_PRINT printf
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#define MBX_WARN_PRINT printf
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#define MBX_INFO_PRINT printf
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#define MBX_DBG_PRINT printf
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#define MBX_WRITEL writel
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#define MBX_READL readl
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#define MBX_UDELAY LOS_Udelay
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#define MBX_MSLEEP LOS_Msleep
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#define MBX_MALLOC(size) LOS_MemAlloc(m_aucSysMem0, size)
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#define MBX_FREE(addr) LOS_MemFree(m_aucSysMem0, addr)
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#define MBX_MUTEX_INIT LOS_MuxCreate
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#define MBX_LIST_ADD(node, head) LOS_ListAdd(head, node)
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#define MBX_LIST_DEL(node) LOS_ListDelete(node)
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#define MBX_INIT_LIST_HEAD LOS_ListInit
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#define MBX_IRQ_RET td_void
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#define MBX_IRQ_HANDLED
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#define MBX_LIST_FOR_EACH_ENTRY(pos, n, head, member) \
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LOS_DL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, struct session, member)
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void init_mailbox_reg(struct session *session, td_u32 session_id, const struct mailbox *mailbox);
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void mbx_polling_rx(void);
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#ifdef __cplusplus
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#if __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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#endif /* _DRV_MAILBOX_H_ */
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