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140 lines
3.5 KiB
140 lines
3.5 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
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* Description: spi-nor and nand universal module
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* Author: Hisilicon
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* Create: 2020-10-15
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*/
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#ifndef NAND_H
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#define NAND_H
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/******************************************************************************/
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#include <stdint.h>
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#include "td_type.h"
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#include "uapi_flash.h"
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#define MTD_ABSENT 0
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#define MTD_RAM 1
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#define MTD_ROM 2
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#define MTD_SPIFLASH 3
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#define MTD_NANDFLASH 4 /* SLC NAND */
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#define MTD_DATAFLASH 6
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#define MTD_UBIVOLUME 7
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#define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */
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#define DEV_MTDBASE "/dev/mtd"
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#define MAX_DEV_NAME_LEN 12
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#define MAX_PART_NAME_LEN 32
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#define PROC_MTD_FILE "/proc/mtd"
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#define STRTOULL_BASE_DEC 10
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#define STRTOULL_BASE_HEX 16
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/*****************************************************************************/
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struct mtd_info_user {
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uint8_t type;
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uint32_t flags;
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uint32_t size;
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uint32_t erasesize;
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uint32_t writesize;
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uint32_t oobsize;
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uint32_t ecctype;
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uint32_t eccsize;
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};
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#define MEMGETINFO _IOR('M', 1, struct mtd_info_user)
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struct erase_info_user64 {
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uint64_t start;
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uint64_t length;
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};
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#define MEMERASE64 _IOW('M', 20, struct erase_info_user64)
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struct mtd_oob_buf {
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uint32_t start;
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uint32_t length;
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td_u8 *ptr;
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};
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#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf)
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/**
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* struct mtd_write_req - data structure for requesting a write operation
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*
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* @start: start address
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* @len: length of data buffer
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* @ooblen: length of OOB buffer
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* @usr_data: user-provided data buffer
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* @usr_oob: user-provided OOB buffer
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* @mode: MTD mode (see "MTD operation modes")
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* @padding: reserved, must be set to 0
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*
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* This structure supports ioctl(MEMWRITE) operations, allowing data and/or OOB
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* writes in various modes. To write to OOB-only, set @usr_data == NULL, and to
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* write data-only, set @usr_oob == NULL. However, setting both @usr_data and
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* @usr_oob to NULL is not allowed.
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*/
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struct mtd_write_req {
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uint64_t start;
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uint64_t len;
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uint64_t ooblen;
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uint64_t usr_data;
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uint64_t usr_oob;
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uint8_t mode;
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uint8_t padding[7]; /* 7 - buffer size */
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};
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#define MEMWRITE _IOWR('M', 24, struct mtd_write_req)
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#define MEMGETBADBLOCK _IOW('M', 11, long long)
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#define MEMSETBADBLOCK _IOW('M', 12, long long)
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#define MEMFORCEERASEBLOCK _IOW('M', 128, long long)
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/*****************************************************************************/
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struct mtd_partition {
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uint64_t start;
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uint64_t end;
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int readonly;
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uapi_flash_access_perm perm;
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char mtddev[MAX_DEV_NAME_LEN];
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char partname[MAX_PART_NAME_LEN];
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td_s32 fd;
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};
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struct nand_raw_ctrl {
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td_s32 num_partition;
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uint64_t size;
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uint32_t pagesize;
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uint32_t blocksize;
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uint32_t oobsize;
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uint32_t oobused;
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uint32_t pageshift;
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uint32_t blockshift;
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uint32_t pagemask;
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uint32_t blockmask;
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struct mtd_partition partition[1];
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};
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#define dbg_out(fmt, arg...)
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td_char *int_to_size(td_u64 size);
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td_s32 get_max_partition(td_void);
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td_s32 offshift(td_ulong n);
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td_s32 flash_partition_info_init(td_void);
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uapi_flash_partinfo *get_flash_partition_info(uapi_flash_type flash_type, const td_char *devname, td_u32 dev_len);
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/******************************************************************************/
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#endif /* NAND_H */
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